On Sun, Jul 23, 2017 at 8:14 PM, Bin Meng <bmeng...@gmail.com> wrote:
> On some flash (like Macronix), QE (quad enable) bit is in the same
> status register as BP# bits, and we need preserve its original value
> during a reboot cycle as this is required by some platforms (like
> Intel ICH SPI controller working under descriptor mode).
>
> Signed-off-by: Bin Meng <bmeng...@gmail.com>
> ---
>
> drivers/mtd/spi/spi_flash.c | 17 +++++++++++++++--
> 1 file changed, 15 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
> index 0034a28..7d8c660 100644
> --- a/drivers/mtd/spi/spi_flash.c
> +++ b/drivers/mtd/spi/spi_flash.c
> @@ -947,11 +947,24 @@ int spi_flash_scan(struct spi_flash *flash)
> if (IS_ERR_OR_NULL(info))
> return -ENOENT;
>
> - /* Flash powers up read-only, so clear BP# bits */
> + /*
> + * Flash powers up read-only, so clear BP# bits.
> + *
> + * Note on some flash (like Macronix), QE (quad enable) bit is in the
> + * same status register as BP# bits, and we need preserve its original
> + * value during a reboot cycle as this is required by some platforms
> + * (like Intel ICH SPI controller working under descriptor mode).
> + */
> if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_ATMEL ||
> - JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX ||
> JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST)
> write_sr(flash, 0);
> + if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX) {
> + u8 sr = 0;
> +
> + read_sr(flash, &sr);
> + sr &= STATUS_QEB_MXIC;
> + write_sr(flash, sr);
> + }
It doesn't make sense to have one(specific) controller fix to be
generic to all macronix chips, think about alternative.
thanks!
--
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
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