On Wed, 26 Jul 2017, Kever Yang wrote:
dwmmc controller has default internal divider by 2, sync code for all Rockchip SoC with: 4055b46 rockchip: clk: rk3288: fix mmc clock setting
While I know that this is the case (i.e. we measured the output frequencies a while back), we should add some documentation/comment to explain where this divider comes from: I didn't see this divider documented in the CRU and the DW-MMC states that setting the SDMMC_CLKDIV to 0 is 'no division, bypass'.
The reason why I am picky about clearly documenting this is that we need to either treat this a a div-2 between the CRU and the DWMMC or capture the fact that the SDMMC_CLKDIV of 0 does not mean 'bypass' (in which case we should double-check that the generic designware MMC driver does not make assumptions that do not apply to us).
Signed-off-by: Kever Yang <kever.y...@rock-chips.com> Acked-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com> --- drivers/clk/rockchip/clk_rk3036.c | 6 +++--- drivers/clk/rockchip/clk_rk3188.c | 4 ++-- drivers/clk/rockchip/clk_rk322x.c | 6 +++--- drivers/clk/rockchip/clk_rk3328.c | 8 ++++---- drivers/clk/rockchip/clk_rk3399.c | 11 +++++++---- 5 files changed, 19 insertions(+), 16 deletions(-)
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