On Wed, 26 Jul 2017, Kever Yang wrote:
mmc using 150000000 as max-frequency and do not use fifo-mode.
Could you expand on the message here (for the benefit of someone reading
this a couple years down the line): did your enabled the FIFO mode now
that the DRAM protection was disabled (which is my guess)?
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com>
---
arch/arm/dts/rk3229-evb.dts | 2 --
arch/arm/dts/rk322x.dtsi | 4 ++--
2 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/rk3229-evb.dts b/arch/arm/dts/rk3229-evb.dts
index 1eac37d..ae0b0a4 100644
--- a/arch/arm/dts/rk3229-evb.dts
+++ b/arch/arm/dts/rk3229-evb.dts
@@ -68,7 +68,6 @@
&emmc {
u-boot,dm-pre-reloc;
- fifo-mode;
status = "okay";
};
@@ -79,7 +78,6 @@
cap-sd-highspeed;
card-detect-delay = <200>;
disable-wp;
- max-frequency = <50000000>;
num-slots = <1>;
supports-sd;
};
diff --git a/arch/arm/dts/rk322x.dtsi b/arch/arm/dts/rk322x.dtsi
index ddbe113..22324f9 100644
--- a/arch/arm/dts/rk322x.dtsi
+++ b/arch/arm/dts/rk322x.dtsi
@@ -388,6 +388,7 @@
sdmmc: dwmmc@30000000 {
compatible = "rockchip,rk3228-dw-mshc",
"rockchip,rk3288-dw-mshc";
reg = <0x30000000 0x4000>;
+ max-frequency = <150000000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
@@ -414,9 +415,8 @@
emmc: dwmmc@30020000 {
compatible = "rockchip,rk3288-dw-mshc";
reg = <0x30020000 0x4000>;
+ max-frequency = <150000000>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <37500000>;
- max-frequency = <37500000>;
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
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