On 04/21/2017 06:37 PM, Dalon Westergreen wrote:
[...]
>>>>> My proposal is revert back to its original code, revert
>>>>> socfpga_bridges_reset() return type to void and don't check error from
>>>>> fpgamgr_test_fpga_ready(). So, we can support Gen5 boot without
>>>>> program FPGA.
>>>>
>>>> Isn't the difference between CV/AV and A10 such that the former can boot
>>>> without programmed FPGA while the later can NOT boot without programmed
>>>> FPGA ? So this code is A10 specific ?
>>>
>>> Yes, at a minimum in A10 the IO ring needs to be configured prior to boot.
>>
>> We do the IOCSR configuration on C5/A5 too, so what's the difference ?
>>
>
> in c5/a5 the iocsr config is done directly, the iocsr data is compiled into
> spl,
> for a10 this is all done by the fpga bitstream, there is no direct iocsr
> config.
So that's why the FPGA must always be programmed with something to get
the A10 working ? I see ... thanks for clarifying.
>>>
>>> Since these functions (socfpga_bridges_reset) are different for c5/a5 and
>>> a10,
>>> i would suggest changing the code to enable the bridges IF the fpga is
>>> configured. perhaps just:
>>
>> If it works ... fine.
>>
>>>
>>> ...
>>> } else
>>> {
>>> writel(0, &sysmgr_regs-
>>>> iswgrp_handoff[0]);
>>> writel(l3mask, &sysmgr_regs-
>>>> iswgrp_handoff[1]);
>>>
>>>
>>> /* Check signal from FPGA.
>>> */
>>> if (!fpgamgr_test_fpga_ready())
>>> {
>>> /* brdmodrst
>>> */
>>> writel(0, &reset_manager_base-
>>>> brg_mod_reset);
>>> }
>>>
>>>
>>>
>>> ...
>>>
>>> I think this actually mirrors the behavior of the 2013.01.01 fork where if
>>> the
>>> fpga is configured, spl enables the bridges.
>>
>> Super :)
>>
>>>
>>> --dalon
>>>
>>
>>
--
Best regards,
Marek Vasut
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