On 17 April 2017 at 21:59, Simon Glass <s...@chromium.org> wrote: > On 17 April 2017 at 09:43, Philipp Tomsich > <philipp.toms...@theobroma-systems.com> wrote: >> This change adds support for configuring the module clocks for SPI1 and >> SPI5 from the 594MHz GPLL. >> >> Note that the driver (rk_spi.c) always sets this to 99MHz, but the >> implemented functionality is more general and will also support >> different clock configurations. >> >> X-AffectedPlatforms: RK3399-Q7 >> Signed-off-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com> >> Tested-by: Jakob Unterwurzacher >> <jakob.unterwurzac...@theobroma-systems.com> >> Tested-by: Klaus Goger <klaus.go...@theobroma-systems.com> >> >> Cover-Letter: > > Odd that this came through - is it the capital L? > > >> rockchip: spi: rk3399: add SPI support for the RK3399 >> >> This series adds SPI support for the RK3399 (SPI1 and SPI5). This >> consists of the following individual changes: >> - clock support for the SPI blocks clocked from GRF (i.e. SPI1, SPI2, >> SPI 4 and SPI5) >> - pinctrl for SPI1 and SPI5 >> - changes the SPI module input clock to 198MHz (instead of 99MHz) for >> the RK3399 to improve the available bitrates at higher frequencies >> (e.g. adding the 39MBit and 28MBit operating points) >> - modifies the calculation of the top frequency permissible (as the >> 49.5MBit operating point had not been permissible due to a hard >> limit at 48MBit) >> END >> >> --- >> >> Changes in v3: >> - replaced macro-pasting with a lookup table to improve readability >> (as requested by Simon) >> >> Changes in v2: >> - fixes a wrong macro usage, which caused the SPI module input clock >> frequency to be significantly higher than intended >> - frequencies have now been validated using an oscilloscope (keep in mind >> that all frequencies are derived from a 99MHz module input clock) at the >> following measurement points (assuming the other fix for the usage of >> DIV_RATE from the series): >> * 1 MHz ... 0.99 MHz >> * 5 MHz ... 4.95 MHz >> * 10 MHz ... 9.9 MHz >> * 30 MHz ... 33 MHz >> * 50 MHz ... 49.5 MHz >> >> drivers/clk/rockchip/clk_rk3399.c | 114 >> ++++++++++++++++++++++++++++++++++++-- >> 1 file changed, 108 insertions(+), 6 deletions(-) > > Acked-by: Simon Glass <s...@chromium.org>
Applied to u-boot-rockchip/next, thanks! _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
