On Wed, Apr 5, 2017 at 4:32 AM, Ley Foon Tan <ley.foon....@intel.com> wrote:
> Restructure clock manager driver in the preparation to support A10.
> Move the Gen5 specific code to _gen5 files.
>
> - Change all uint32_t to u32 and change to use macro BIT(n) for bit shift.
> - Check return value from wait_for_bit(). So change return type to int for
> cm_write_with_phase() and cm_basic_init().
>
> Signed-off-by: Ley Foon Tan <ley.foon....@intel.com>
> ---
> arch/arm/mach-socfpga/Makefile | 3 +-
> arch/arm/mach-socfpga/clock_manager.c | 515
> +--------------------
> .../{clock_manager.c => clock_manager_gen5.c} | 137 ++----
> arch/arm/mach-socfpga/include/mach/clock_manager.h | 316 +------------
> .../mach/{clock_manager.h => clock_manager_gen5.h} | 151 +++---
> arch/arm/mach-socfpga/spl.c | 5 +-
> 6 files changed, 151 insertions(+), 976 deletions(-)
> copy arch/arm/mach-socfpga/{clock_manager.c => clock_manager_gen5.c} (85%)
> copy arch/arm/mach-socfpga/include/mach/{clock_manager.h =>
> clock_manager_gen5.h} (79%)
>
[snip]
> debug("Reconfigure Clock Manager\n");
> /* reconfigure the PLLs */
> - cm_basic_init(cm_default_cfg);
> + if (cm_basic_init(cm_default_cfg)) {
> + puts("Clock setup failed.\n");
If the clock configuration has failed, would you be able to print
anything to the uart?
> + hang();
> + }
>
> /* Enable bootrom to configure IOs. */
> sysmgr_config_warmrstcfgio(1);
Dinh
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