On 02/22/2017 10:47 AM, Ley Foon Tan wrote: > Add system manager support for Arria 10.
But these are just headers, there's no system manager code here ? > Signed-off-by: Tien Fong Chee <tien.fong.c...@intel.com> > Signed-off-by: Ley Foon Tan <ley.foon....@intel.com> > --- > .../arm/mach-socfpga/include/mach/system_manager.h | 54 ++++++++++++++- > .../include/mach/system_manager_arria10.h | 81 > ++++++++++++++++++++++ > .../include/mach/system_manager_gen5.h | 1 + > 3 files changed, 135 insertions(+), 1 deletion(-) > create mode 100755 > arch/arm/mach-socfpga/include/mach/system_manager_arria10.h > > diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h > b/arch/arm/mach-socfpga/include/mach/system_manager.h > index 53ced81..324d13f 100644 > --- a/arch/arm/mach-socfpga/include/mach/system_manager.h > +++ b/arch/arm/mach-socfpga/include/mach/system_manager.h > @@ -31,7 +31,59 @@ > #define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB 2 > #define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x3 > > -#if defined(CONFIG_TARGET_SOCFPGA_GEN5) > +/* For dedicated IO configuration */ > +/* Voltage select enums */ > +#define VOLTAGE_SEL_3V 0x0 > +#define VOLTAGE_SEL_1P8V 0x1 > +#define VOLTAGE_SEL_2P5V 0x2 > + > +/* Input buffer enable */ > +#define INPUT_BUF_DISABLE 0 > +#define INPUT_BUF_1P8V 1 > +#define INPUT_BUF_2P5V3V 2 > + > +/* Weak pull up enable */ > +#define WK_PU_DISABLE 0 > +#define WK_PU_ENABLE 1 > + > +/* Pull up slew rate control */ > +#define PU_SLW_RT_SLOW 0 > +#define PU_SLW_RT_FAST 1 > +#define PU_SLW_RT_DEFAULT PU_SLW_RT_SLOW > + > +/* Pull down slew rate control */ > +#define PD_SLW_RT_SLOW 0 > +#define PD_SLW_RT_FAST 1 > +#define PD_SLW_RT_DEFAULT PD_SLW_RT_SLOW > + > +/* Drive strength control */ > +#define PU_DRV_STRG_DEFAULT 0x10 > +#define PD_DRV_STRG_DEFAULT 0x10 > + > +/* bit position */ > +#define PD_DRV_STRG_LSB 0 > +#define PD_SLW_RT_LSB 5 > +#define PU_DRV_STRG_LSB 8 > +#define PU_SLW_RT_LSB 13 > +#define WK_PU_LSB 16 > +#define INPUT_BUF_LSB 17 > +#define BIAS_TRIM_LSB 19 > +#define VOLTAGE_SEL_LSB 0 > + > +#define ALT_SYSMGR_NOC_H2F_SET_MSK 0x00000001 > +#define ALT_SYSMGR_NOC_LWH2F_SET_MSK 0x00000010 > +#define ALT_SYSMGR_NOC_F2H_SET_MSK 0x00000100 > +#define ALT_SYSMGR_NOC_F2SDR0_SET_MSK 0x00010000 > +#define ALT_SYSMGR_NOC_F2SDR1_SET_MSK 0x00100000 > +#define ALT_SYSMGR_NOC_F2SDR2_SET_MSK 0x01000000 > +#define ALT_SYSMGR_NOC_TMO_EN_SET_MSK 0x00000001 > + > +#define ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM_SET_MSK 0x00000002 > +#define ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM_SET_MSK 0x00000002 > + > +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) > +#include <asm/arch/system_manager_arria10.h> > +#elif defined(CONFIG_TARGET_SOCFPGA_GEN5) > #include <asm/arch/system_manager_gen5.h> > #endif > > diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h > b/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h > new file mode 100755 > index 0000000..78432ec > --- /dev/null > +++ b/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h > @@ -0,0 +1,81 @@ > +/* > + * Copyright (C) 2013-2017 Altera Corporation <www.altera.com> > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#ifndef _SYSTEM_MANAGER_ARRIA10_H_ > +#define _SYSTEM_MANAGER_ARRIA10_H_ > + > +struct socfpga_system_manager { > + u32 siliconid1; > + u32 siliconid2; > + u32 wddbg; > + u32 bootinfo; > + u32 mpu_ctrl_l2_ecc; > + u32 _pad_0x14_0x1f[3]; > + u32 dma; > + u32 dma_periph; > + u32 sdmmcgrp_ctrl; > + u32 sdmmc_l3master; > + u32 nand_bootstrap; > + u32 nand_l3master; > + u32 usb0_l3master; > + u32 usb1_l3master; > + u32 emac_global; > + u32 emac[3]; > + u32 _pad_0x50_0x5f[4]; > + u32 fpgaintf_en_global; > + u32 fpgaintf_en_0; > + u32 fpgaintf_en_1; > + u32 fpgaintf_en_2; > + u32 fpgaintf_en_3; > + u32 _pad_0x74_0x7f[3]; > + u32 noc_addr_remap_value; > + u32 noc_addr_remap_set; > + u32 noc_addr_remap_clear; > + u32 _pad_0x8c_0x8f; > + u32 ecc_intmask_value; > + u32 ecc_intmask_set; > + u32 ecc_intmask_clr; > + u32 ecc_intstatus_serr; > + u32 ecc_intstatus_derr; > + u32 mpu_status_l2_ecc; > + u32 mpu_clear_l2_ecc; > + u32 mpu_status_l1_parity; > + u32 mpu_clear_l1_parity; > + u32 mpu_set_l1_parity; > + u32 _pad_0xb8_0xbf[2]; > + u32 noc_timeout; > + u32 noc_idlereq_set; > + u32 noc_idlereq_clr; > + u32 noc_idlereq_value; > + u32 noc_idleack; > + u32 noc_idlestatus; > + u32 fpga2soc_ctrl; > + u32 _pad_0xdc_0xff[9]; > + u32 tsmc_tsel_0; > + u32 tsmc_tsel_1; > + u32 tsmc_tsel_2; > + u32 tsmc_tsel_3; > + u32 _pad_0x110_0x200[60]; > + u32 romhw_ctrl; > + u32 romcode_ctrl; > + u32 romcode_cpu1startaddr; > + u32 romcode_initswstate; > + u32 romcode_initswlastld; > + u32 _pad_0x214_0x217; > + u32 warmram_enable; > + u32 warmram_datastart; > + u32 warmram_length; > + u32 warmram_execution; > + u32 warmram_crc; > + u32 _pad_0x22c_0x22f; > + u32 isw_handoff[8]; > + u32 romcode_bootromswstate[8]; > +}; > + > +#define SYSMGR_SDMMC_SMPLSEL_SHIFT 4 > +#define SYSMGR_BOOTINFO_BSEL_SHIFT 12 > + > +#endif /* _SYSTEM_MANAGER_ARRIA10_H_ */ > diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h > b/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h > index 3ad4ca1..285c1a2 100755 > --- a/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h > +++ b/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h > @@ -117,5 +117,6 @@ struct socfpga_system_manager { > #endif > > #define SYSMGR_SDMMC_SMPLSEL_SHIFT 3 > +#define SYSMGR_BOOTINFO_BSEL_SHIFT 0 > > #endif /* _SYSTEM_MANAGER_GEN5_H_ */ > -- Best regards, Marek Vasut _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot