On 02/22/2017 10:47 AM, Ley Foon Tan wrote: > Restructure clock manager driver in the preparation to support A10. > Move the Gen5 specific code to _gen5 files. No functional change. > > Change all uint32_t to u32 and change to use macro BIT(n) for bit shift. > > Signed-off-by: Ley Foon Tan <ley.foon....@intel.com>
[...] > --- a/arch/arm/mach-socfpga/clock_manager.c > +++ b/arch/arm/mach-socfpga/clock_manager.c > @@ -1,5 +1,5 @@ > /* > - * Copyright (C) 2013 Altera Corporation <www.altera.com> > + * Copyright (C) 2013-2017 Altera Corporation <www.altera.com> > * > * SPDX-License-Identifier: GPL-2.0+ > */ > @@ -13,10 +13,10 @@ DECLARE_GLOBAL_DATA_PTR; > static const struct socfpga_clock_manager *clock_manager_base = > (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS; > > -static void cm_wait_for_lock(uint32_t mask) > +void cm_wait_for_lock(u32 mask) > { > - register uint32_t inter_val; We should probably drop this "register" altogether. > - uint32_t retry = 0; > + register u32 inter_val; > + u32 retry = 0; > do { > inter_val = readl(&clock_manager_base->inter) & mask; > if (inter_val == mask) [...] > static void cm_print_clock_quick_summary(void) > { > printf("MPU %10ld kHz\n", cm_get_mpu_clk_hz() / 1000); > diff --git a/arch/arm/mach-socfpga/clock_manager_gen5.c > b/arch/arm/mach-socfpga/clock_manager_gen5.c > new file mode 100755 > index 0000000..1df2ed4 > --- /dev/null > +++ b/arch/arm/mach-socfpga/clock_manager_gen5.c > @@ -0,0 +1,495 @@ > +/* > + * Copyright (C) 2013-2017 Altera Corporation <www.altera.com> > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#include <common.h> > +#include <asm/io.h> > +#include <asm/arch/clock_manager.h> > + > +DECLARE_GLOBAL_DATA_PTR; > + > +static const struct socfpga_clock_manager *clock_manager_base = > + (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS; > + > +/* > + * function to write the bypass register which requires a poll of the > + * busy bit > + */ > +static void cm_write_bypass(u32 val) > +{ > + writel(val, &clock_manager_base->bypass); > + cm_wait_for_fsm(); > +} > + > +/* function to write the ctrl register which requires a poll of the busy bit > */ > +static void cm_write_ctrl(u32 val) > +{ > + writel(val, &clock_manager_base->ctrl); > + cm_wait_for_fsm(); > +} > + > +/* function to write a clock register that has phase information */ > +static void cm_write_with_phase(u32 value, > + u32 reg_address, u32 mask) > +{ > + /* poll until phase is zero */ > + while (readl(reg_address) & mask) > + ; This polling should be bounded, in fact, wait_for_bit() might be what you want . > + writel(value, reg_address); > + > + while (readl(reg_address) & mask) > + ; DTTO > +} > + > +/* > + * Setup clocks while making no assumptions about previous state of the > clocks. [...] -- Best regards, Marek Vasut _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot