On 2/24/2017 12:55 AM, Marek Vasut wrote: > On 02/23/2017 08:22 PM, Rush, Jason A. wrote: >> Marek Vasut wrote: >>> On 02/22/2017 06:37 PM, Rush, Jason A. wrote: >>>> Marek Vasut wrote: >>>>> On 02/21/2017 05:50 PM, Rush, Jason A. wrote: [...] >> >> While I was debugging some of my changes, I noticed that the data being read >> from the >> QSPI flash device appears to be random. The CPU no longer resets while >> performing a >> read when the indirect trigger address is setup correctly for the Altrera >> SoC, but there >> appears to be a larger problem with reading data in general. >>
How random is it? Is the problem seen only when unaligned read/write are done or when length of transfer is not a multiple of word(4 byte)? If the data is really random in all cases, then I suspect timing issues. Please see if delay values are populated correctly in DT. >> When I apply my patch to the v2016.11 release, reads appear correct. >> However, when I >> apply my patch to the v2017.01 release, the data read from the QSPI device >> appear to be >> random/corrupt. I noticed the cadence_spi_apb.c file changed significantly >> between >> v2016.11 and v2017.01, possibly a change in this file is causing the problem >> on the Altera >> SoC. >> >> I'm not really that familiar with the cadence device, so this issue is >> getting a little beyond a >> simple patch to setup the indirect trigger address correctly for the Altrera >> SoC. Is there >> anyone more familiar with the cadence device on the Altera SoC that could >> take a look >> into this? > > Vignesh did those changes, so I think he can assist you. In the > meantime, you can try git bisect . Another thing you can try is > disabling the dcache and see if that fixes things (dcache off), > I recall seeing some caching issues with CQSPI. > You could try reverting my commits: commit 57897c13de03ac0136d64641a3eab526c6810387 spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible commit b63b46313ed29e9b0c36b3d6b9407f6eade40c8f spi: cadence_qspi_apb: Use 32 bit indirect read transaction when possible But there were other patches by others in v2017.01-rc1, like spi: cadence_qspi: Fix CS timings which may have impact. -- Regards Vignesh _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
