From: Prabhakar Kushwaha
>> From: U-Boot [mailto:[email protected]] On Behalf Of york
>> On 06/30/2016 02:03 AM, Gong Qianyu wrote:
>> > From: Mingkai Hu <[email protected]>
>> >
>> > Data coherency is enabled only when the CPUECTLR.SMPEN bit is set.
>> > The SMPEN bit should be set before enabling the data cache.
>> > If not enabled, the cache is not coherent with other cores and data
>> > corruption could occur.
>> >
>> > + /* Enalbe SMPEN bit */
>> > + mrs x0, S3_1_c15_c2_1 /* cpuactlr_el1 */
>> > + orr x0, x0, #0x40
>> > + msr S3_1_c15_c2_1, x0
>> > +
>>
>> I wonder what impact this patch has. Did you find it effective on A53 core?
>> According to ARM documents, A57 and A72 seem don't care this bit.
>
>I have seen big difference on LS1012A with A53 cores after enabling this bit.
>If I don't enable this bit many IPs like SATA, SDHC show coherency issue.
But LS1012A only has a single A53 core.
The multicore part, LS1043A, sets this bit in the bootrom:
34: d539f221 mrs x1, s3_1_c15_c2_1
38: b27a0021 orr x1, x1, #0x40
3c: d519f221 msr s3_1_c15_c2_1, x1
Ed
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