Hi York,
> -----Original Message----- > From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of york sun > Sent: Thursday, June 30, 2016 10:32 PM > To: Qianyu Gong <qianyu.g...@nxp.com>; albert.u.b...@aribaud.net; u- > b...@lists.denx.de; s.temerkha...@gmail.com; > yamada.masah...@socionext.com > Cc: Mingkai Hu <mingkai...@nxp.com> > Subject: Re: [U-Boot] [PATCH] armv8: Enable CPUECTLR.SMPEN for data > coherency > > On 06/30/2016 02:03 AM, Gong Qianyu wrote: > > From: Mingkai Hu <mingkai...@nxp.com> > > > > Data coherency is enabled only when the CPUECTLR.SMPEN bit is set. The > > SMPEN bit should be set before enabling the data cache. > > If not enabled, the cache is not coherent with other cores and data > > corruption could occur. > > > > Signed-off-by: Mingkai Hu <mingkai...@nxp.com> > > Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com> > > > > diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S > > index 670e323..735dd67 100644 > > --- a/arch/arm/cpu/armv8/start.S > > +++ b/arch/arm/cpu/armv8/start.S > > @@ -81,6 +81,11 @@ reset: > > msr cpacr_el1, x0 /* Enable FP/SIMD */ > > 0: > > > > + /* Enalbe SMPEN bit */ > > + mrs x0, S3_1_c15_c2_1 /* cpuactlr_el1 */ > > + orr x0, x0, #0x40 > > + msr S3_1_c15_c2_1, x0 > > + > > /* Apply ARM core specific erratas */ > > bl apply_core_errata > > > > > > Qianyu, > > I wonder what impact this patch has. Did you find it effective on A53 core? > According to ARM documents, A57 and A72 seem don't care this bit. > Quote > I have seen big difference on LS1012A with A53 cores after enabling this bit. If I don't enable this bit many IPs like SATA, SDHC show coherency issue. --prabhakar _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
