On Monday 07 September 2009 15:57:19 Wouter Eckhardt wrote:
> Well, I've been trying to work this into my U-Boot. I haven't succeeded
> so far. Basically, the cache stuff in 4xx_spd_ddr2.c consists of setting
> up a TLB without the CACHE_INHIBITED bit and then using some cache
> instructions to fill up memory. That's what I've been trying to do, but
> my call to change_tlb() hangs because of the invalidate_dcache() call
> (bad trap exceptions). What could be going on here?
>
> I'll try and set up the DDR TLB dynamically instead of statically (in
> init.S) and see if I can get that working.
Yes. That's what I would do as well.
> By the way, I've also stumbled upon some other VERY strange behavior. If
> I leave the ecc_init() in its original state and just add in a puts(" ")
> call at the beginning of the function, ECC generation is finished VERY
> quickly. What influence could adding the puts() call possibly have on
> the speed of generating ECC values in DDR?
That's strange indeed. I suspect a problem in the code then. Try looking at
the generated assembler code and/or debug with an BDI2000/3000.
Cheers,
Stefan
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