Hi Stefan, Thanks for the quick reply.
> > 2009.03 is already "old". I suggest you use the 2009.09 release. > Okay, shouldn't be too much trouble. (You actually meant .08, right? :-) > > d-cache is the solution. > That's what I thought as well. Seems that coming up with the solution was a bit easier than actually implementing it... > > Did you flush the caches? You need to be careful here, when changing TLB > attributes. > > Which DDR2 init code are you using btw? A specific custom code with fixed > settings? Or the 4xx common SPD code? I suggest you take a look at the > common > DDR2 code (44x_spd_ddr2.c). ECC handling is done there already with caches > enabled. This should give you an idea. I didn't flush the cache (seemed a bit pointless since they're not in use at that point anyway, right?). I'll give it a whirl. I'll also look into the other ECC initialization. I actually thought ECC initialization was only done in sdram.c (after a quick search for CONFIG_SDRAM_ECC). That probably also answers your next question. My SDRAM initialization is the same one as is used for the ALPR board and that uses the common code, as far as I know. Kind regards, Wouter Eckhardt. Disclaimer: The information contained in this email, including any attachments is confidential and is for the sole use of the intended recipient(s). Any unauthorized review, use, disclosure or distribution is prohibited. If you are not the intended recipient, please notify the sender immediately by replying to this message and destroy all copies of this message and any attachments. _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
