Hi Stefan,
> > I didn't flush the cache (seemed a bit pointless since they're not
in
> > use at that point anyway, right?). I'll give it a whirl. I'll also
look
> > into the other ECC initialization.
>
> Good.
>
> > I actually thought ECC initialization was only done in sdram.c
(after a
> > quick search for CONFIG_SDRAM_ECC). That probably also answers your
next
> > question. My SDRAM initialization is the same one as is used for the
> > ALPR board and that uses the common code, as far as I know.
>
> Right. After looking at it, the ECC init is done in this common file.
But
> the
> cache handling is missing here. I suggest you try to port this stuff
from
> the
> DDR2 init file I mentioned in my last mail.
Well, I've been trying to work this into my U-Boot. I haven't succeeded
so far. Basically, the cache stuff in 4xx_spd_ddr2.c consists of setting
up a TLB without the CACHE_INHIBITED bit and then using some cache
instructions to fill up memory. That's what I've been trying to do, but
my call to change_tlb() hangs because of the invalidate_dcache() call
(bad trap exceptions). What could be going on here?
I'll try and set up the DDR TLB dynamically instead of statically (in
init.S) and see if I can get that working.
By the way, I've also stumbled upon some other VERY strange behavior. If
I leave the ecc_init() in its original state and just add in a puts(" ")
call at the beginning of the function, ECC generation is finished VERY
quickly. What influence could adding the puts() call possibly have on
the speed of generating ECC values in DDR?
Kind regards,
Wouter Eckhardt.
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