We need reset the Ethernet Switch analog part before operation,
or the build-in Ethernet PHY don't work.
Signed-off-by: Wills Wang <wills.w...@live.com>
---
arch/mips/mach-ath79/include/mach/ar71xx_regs.h | 1 +
arch/mips/mach-ath79/reset.c | 3 ++-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
index a8e51cb..dabcad0 100644
--- a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
+++ b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
@@ -660,6 +660,7 @@
#define AR933X_RESET_GE1_MDIO BIT(23)
#define AR933X_RESET_GE0_MDIO BIT(22)
+#define AR933X_RESET_ETH_SWITCH_ANALOG BIT(14)
#define AR933X_RESET_GE1_MAC BIT(13)
#define AR933X_RESET_WMAC BIT(11)
#define AR933X_RESET_GE0_MAC BIT(9)
diff --git a/arch/mips/mach-ath79/reset.c b/arch/mips/mach-ath79/reset.c
index 188eccb..a88bcbc 100644
--- a/arch/mips/mach-ath79/reset.c
+++ b/arch/mips/mach-ath79/reset.c
@@ -81,7 +81,8 @@ static int eth_init_ar933x(void)
MAP_NOCACHE);
const u32 mask = AR933X_RESET_GE0_MAC | AR933X_RESET_GE0_MDIO |
AR933X_RESET_GE1_MAC | AR933X_RESET_GE1_MDIO |
- AR933X_RESET_ETH_SWITCH;
+ AR933X_RESET_ETH_SWITCH |
+ AR933X_RESET_ETH_SWITCH_ANALOG;
/* Clear MDIO slave EN bit. */
clrbits_be32(rregs + AR933X_RESET_REG_BOOTSTRAP, BIT(17));
--
1.9.1
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