Hi Bin,
On 11 March 2016 at 01:30, Bin Meng <bmeng...@gmail.com> wrote:
> Hi Simon,
>
> On Mon, Mar 7, 2016 at 10:28 AM, Simon Glass <s...@chromium.org> wrote:
>> Broadwell uses a binary blob called the memory reference code (MRC) to start
>> up its SDRAM. This is similar to ivybridge so we can mostly use common code
>> for running this blob.
>>
>> Signed-off-by: Simon Glass <s...@chromium.org>
>> ---
>>
>> arch/x86/cpu/broadwell/Makefile | 1 +
>> arch/x86/cpu/broadwell/sdram.c | 307
>> +++++++++++++++++++++++++
>> arch/x86/include/asm/arch-broadwell/pei_data.h | 177 ++++++++++++++
>> arch/x86/include/asm/global_data.h | 24 ++
>> 4 files changed, 509 insertions(+)
>> create mode 100644 arch/x86/cpu/broadwell/sdram.c
>> create mode 100644 arch/x86/include/asm/arch-broadwell/pei_data.h
>>
>> diff --git a/arch/x86/cpu/broadwell/Makefile
>> b/arch/x86/cpu/broadwell/Makefile
>> index 5a62afa..012798f 100644
>> --- a/arch/x86/cpu/broadwell/Makefile
>> +++ b/arch/x86/cpu/broadwell/Makefile
>> @@ -13,3 +13,4 @@ obj-y += pinctrl_broadwell.o
>> obj-y += power_state.o
>> obj-y += refcode.o
>> obj-y += sata.o
>> +obj-y += sdram.o
>> diff --git a/arch/x86/cpu/broadwell/sdram.c b/arch/x86/cpu/broadwell/sdram.c
>> new file mode 100644
>> index 0000000..caf6ef6
>> --- /dev/null
>> +++ b/arch/x86/cpu/broadwell/sdram.c
>> @@ -0,0 +1,307 @@
>> +/*
>> + * Copyright (c) 2016 Google, Inc
>> + *
>> + * From coreboot src/soc/intel/broadwell/romstage/raminit.c
>> + *
>> + * SPDX-License-Identifier: GPL-2.0
>
> nits: GPL-2.0+?
>
>> + */
>> +
>> +#include <common.h>
>> +#include <dm.h>
>> +#include <pci.h>
>> +#include <syscon.h>
>> +#include <asm/cpu.h>
>> +#include <asm/io.h>
>> +#include <asm/lpc_common.h>
>> +#include <asm/mrccache.h>
>> +#include <asm/mtrr.h>
>> +#include <asm/pci.h>
>> +#include <asm/sdram_common.h>
>> +#include <asm/arch/iomap.h>
>> +#include <asm/arch/me.h>
>> +#include <asm/arch/pch.h>
>> +#include <asm/arch/pei_data.h>
>> +#include <asm/arch/pm.h>
[snip]
>> diff --git a/arch/x86/include/asm/arch-broadwell/pei_data.h
>> b/arch/x86/include/asm/arch-broadwell/pei_data.h
>> new file mode 100644
>> index 0000000..b2cc8b8
>> --- /dev/null
>> +++ b/arch/x86/include/asm/arch-broadwell/pei_data.h
>> @@ -0,0 +1,177 @@
>> +/*
>> + * From Coreboot soc/intel/broadwell/include/soc/pei_data.h
>> + *
>> + * Copyright (C) 2014 Google Inc.
>> + *
>> + * SPDX-License-Identifier: BSD-3-Clause
>> + */
>> +
>> +#ifndef ASM_ARCH_PEI_DATA_H
>> +#define ASM_ARCH_PEI_DATA_H
>> +
>> +#include <linux/linkage.h>
>> +
>> +#define PEI_VERSION 22
>> +
[snip]
>>
>> +struct dimm_info {
>> + uint32_t dimm_size;
>> + uint16_t ddr_type;
>> + uint16_t ddr_frequency;
>> + uint8_t rank_per_dimm;
>> + uint8_t channel_num;
>> + uint8_t dimm_num;
>> + uint8_t bank_locator;
>> + /* The 5th byte is '\0' for the end of string */
>> + uint8_t serial[5];
>> + /* The 19th byte is '\0' for the end of string */
>> + uint8_t module_part_number[19];
>> + uint16_t mod_id;
>> + uint8_t mod_type;
>> + uint8_t bus_width;
>> +} __packed;
>> +
>> +struct pei_memory_info {
>> + uint8_t dimm_cnt;
>> + /* Maximum num of dimm is 8 */
>> + struct dimm_info dimm[8];
>> +} __packed;
>
> I am thinking whether we can put these platform specific structures to
> somewhere else? It looks the broadwell is using different memory_info
> from ivybridge.
Where should they go? This file is for broadwell - ivybridge could
have its own if we need it.
Regards,
Simon
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