The arch/arm/lib/cache-cp15.c checks for CONFIG_ARMV7 and if this macro is
set, it configures TTBR0 register. This register must be configured for the
cache on ARMv7 to operate correctly.
The problem is that noone actually sets the CONFIG_ARMV7 macro and thus the
TTBR0 is not configured at all. On SoCFPGA, this produces all sorts of minor
issues which are hard to replicate, for example certain USB sticks are not
detected or QSPI NOR sometimes fails to write pages completely.
Signed-off-by: Marek Vasut <ma...@denx.de>
Cc: Tom Rini <tr...@konsulko.com>
Cc: Albert Aribaud <albert.u.b...@aribaud.net>
Cc: Simon Glass <s...@chromium.org>
---
arch/arm/Kconfig | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index fb9176b..c0ab947 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -4,6 +4,9 @@ menu "ARM architecture"
config SYS_ARCH
default "arm"
+config ARMV7
+ bool
+
config ARM64
bool
@@ -34,11 +37,13 @@ config CPU_ARM1176
config CPU_V7
bool
+ select ARMV7
select HAS_VBAR
select HAS_THUMB2
config CPU_V7M
bool
+ select ARMV7
select HAS_THUMB2
config CPU_PXA
--
2.1.4
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