From: Alex Dubov <oa...@yahoo.com>
Move board definition files for STx XTC, GP3 and SSA boards into
common subdirectory and factor out common code.
"-mno-spe" flag common to all MPC85xx configurations does not work
so change it to "-mspe=no" which does (GCC bug 37759).
Signed-off-by: Alex Dubov <oa...@yahoo.com>
---
Makefile | 6 +-
board/{stxgp3 => stx/common}/Makefile | 20 +++--
board/{stxssa => stx/common}/ddr.c | 46 ++++++++---
board/{stxssa => stx/common}/law.c | 30 ++++---
board/{stxssa => stx/common}/tlb.c | 72 ++++++++++-------
board/{ => stx}/stxgp3/Makefile | 3 -
board/{ => stx}/stxgp3/config.mk | 0
board/{ => stx}/stxgp3/flash.c | 0
board/{ => stx}/stxgp3/stxgp3.c | 0
board/{ => stx}/stxgp3/u-boot.lds | 0
board/{ => stx}/stxssa/Makefile | 3 -
board/{ => stx}/stxssa/config.mk | 0
board/{ => stx}/stxssa/stxssa.c | 0
board/{ => stx}/stxssa/u-boot.lds | 0
board/{ => stx}/stxxtc/Makefile | 0
board/{ => stx}/stxxtc/config.mk | 0
board/{ => stx}/stxxtc/stxxtc.c | 0
board/{ => stx}/stxxtc/u-boot.lds | 0
board/{ => stx}/stxxtc/u-boot.lds.debug | 0
board/stxgp3/ddr.c | 76 ------------------
board/stxgp3/law.c | 58 --------------
board/stxgp3/tlb.c | 130 -------------------------------
cpu/mpc85xx/config.mk | 2 +-
include/configs/stxgp3.h | 21 +++--
include/configs/stxssa.h | 28 ++++---
25 files changed, 135 insertions(+), 360 deletions(-)
copy board/{stxgp3 => stx/common}/Makefile (82%)
rename board/{stxssa => stx/common}/ddr.c (57%)
rename board/{stxssa => stx/common}/law.c (74%)
rename board/{stxssa => stx/common}/tlb.c (59%)
rename board/{ => stx}/stxgp3/Makefile (95%)
rename board/{ => stx}/stxgp3/config.mk (100%)
rename board/{ => stx}/stxgp3/flash.c (100%)
rename board/{ => stx}/stxgp3/stxgp3.c (100%)
rename board/{ => stx}/stxgp3/u-boot.lds (100%)
rename board/{ => stx}/stxssa/Makefile (95%)
rename board/{ => stx}/stxssa/config.mk (100%)
rename board/{ => stx}/stxssa/stxssa.c (100%)
rename board/{ => stx}/stxssa/u-boot.lds (100%)
rename board/{ => stx}/stxxtc/Makefile (100%)
rename board/{ => stx}/stxxtc/config.mk (100%)
rename board/{ => stx}/stxxtc/stxxtc.c (100%)
rename board/{ => stx}/stxxtc/u-boot.lds (100%)
rename board/{ => stx}/stxxtc/u-boot.lds.debug (100%)
delete mode 100644 board/stxgp3/ddr.c
delete mode 100644 board/stxgp3/law.c
delete mode 100644 board/stxgp3/tlb.c
diff --git a/Makefile b/Makefile
index 8096f91..a445eba 100644
--- a/Makefile
+++ b/Makefile
@@ -1129,7 +1129,7 @@ SPD823TS_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc8xx spd8xx
stxxtc_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8xx stxxtc
+ @$(MKCONFIG) $(@:_config=) ppc mpc8xx stxxtc stx
svm_sc8xx_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc8xx svm_sc8xx
@@ -2526,7 +2526,7 @@ socrates_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx socrates
stxgp3_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc85xx stxgp3
+ @$(MKCONFIG) $(@:_config=) ppc mpc85xx stxgp3 stx
stxssa_config \
stxssa_4M_config: unconfig
@@ -2535,7 +2535,7 @@ stxssa_4M_config: unconfig
echo "#define CONFIG_STXSSA_4M" >>$(obj)include/config.h ; \
$(XECHO) "... with 4 MiB flash memory" ; \
fi
- @$(MKCONFIG) -a stxssa ppc mpc85xx stxssa
+ @$(MKCONFIG) -a stxssa ppc mpc85xx stxssa stx
TQM8540_config \
TQM8541_config \
diff --git a/board/stxgp3/Makefile b/board/stx/common/Makefile
similarity index 82%
copy from board/stxgp3/Makefile
copy to board/stx/common/Makefile
index 5a68f11..08cc2f9 100644
--- a/board/stxgp3/Makefile
+++ b/board/stx/common/Makefile
@@ -1,5 +1,5 @@
#
-# (C) Copyright 2001-2006
+# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
#
# See file CREDITS for list of people who contributed to this
@@ -23,23 +23,25 @@
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)board/$(VENDOR)/common)
+endif
-COBJS-y += $(BOARD).o
-COBJS-y += law.o
-COBJS-y += tlb.o
-COBJS-y += flash.o
-COBJS-$(CONFIG_FSL_DDR1) += ddr.o
+LIB = $(obj)lib$(VENDOR).a
+
+COBJS-${CONFIG_MPC85xx} += ddr.o
+COBJS-${CONFIG_MPC85xx} += law.o
+COBJS-${CONFIG_MPC85xx} += tlb.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
clean:
- rm -f $(OBJS) $(SOBJS)
+ rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
diff --git a/board/stxssa/ddr.c b/board/stx/common/ddr.c
similarity index 57%
rename from board/stxssa/ddr.c
rename to board/stx/common/ddr.c
index 93d1100..5e7b184 100644
--- a/board/stxssa/ddr.c
+++ b/board/stx/common/ddr.c
@@ -1,5 +1,6 @@
/*
* Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2009 Alex Dubov <oa...@yahoo.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@@ -13,31 +14,33 @@
#include <asm/fsl_ddr_dimm_params.h>
static void
-get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address)
+get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
{
+#if defined(CONFIG_FSL_DDR2)
+ i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
+#elif defined(CONFIG_FSL_DDR1)
i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t));
+#else
+#error DDR type is not defined
+#endif
}
-
-unsigned int
-fsl_ddr_get_mem_data_rate(void)
+unsigned int fsl_ddr_get_mem_data_rate(void)
{
return get_ddr_freq(0);
}
-
-void
-fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd,
- unsigned int ctrl_num)
+void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num)
{
unsigned int i;
- unsigned int i2c_address = 0;
+
+ if (ctrl_num) {
+ printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
+ return;
+ }
for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
- if (ctrl_num == 0 && i == 0) {
- i2c_address = SPD_EEPROM_ADDRESS;
- }
- get_spd(&(ctrl_dimms_spd[i]), i2c_address);
+ get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS);
}
}
@@ -46,11 +49,28 @@ void fsl_ddr_board_options(memctl_options_t *popts,
unsigned int ctrl_num)
{
/*
+ * Factors to consider for clock adjust:
+ * - number of chips on bus
+ * - position of slot
+ * - DDR1 vs. DDR2?
+ * - ???
+ *
+ * This needs to be determined on a board-by-board basis.
+ * 0110 3/4 cycle late
+ * 0111 7/8 cycle late
+ */
+ popts->clk_adjust = 6;
+
+ /*
* Factors to consider for CPO:
* - frequency
* - ddr1 vs. ddr2
*/
+#if defined(CONFIG_FSL_DDR2)
+ popts->cpo_override = 7;
+#else
popts->cpo_override = 0;
+#endif
/*
* Factors to consider for write data delay:
diff --git a/board/stxssa/law.c b/board/stx/common/law.c
similarity index 74%
rename from board/stxssa/law.c
rename to board/stx/common/law.c
index 55dde66..a82c99f 100644
--- a/board/stxssa/law.c
+++ b/board/stx/common/law.c
@@ -1,9 +1,9 @@
/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, w...@denx.de.
*
+ * Copyright 2009 Alex Dubov <oa...@yahoo.com>
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
@@ -31,30 +31,34 @@
* LAW(Local Access Window) configuration:
*
* 0x0000_0000 0x7fff_ffff DDR 2G
- * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
- * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
+ * 0x8000_0000 0x9fff_ffff PCI1 512M
+ * 0xa000_0000 0xbfff_ffff PCI2 512M
+ * 0xc000_0000 0xdfff_ffff RapidIO 512M
* 0xe000_0000 0xe000_ffff CCSR 1M
* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
* 0xe300_0000 0xe3ff_ffff PCI2 IO 16M
- * 0xf000_0000 0xfaff_ffff Local bus 128M
- * 0xfb00_0000 0xfb00_ffff Config Latch 64K
- * 0xfc00_0000 0xffff_ffff FLASH (boot bank) 64M
+ * 0xf000_0000 0xffff_ffff LBC options + FLASH 256M
*
* Notes:
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
* If flash is 8M at default position (last 8M), no LAW needed.
+ *
+ * LAW 0 is reserved for boot mapping
*/
struct law_entry law_table[] = {
-#ifndef CONFIG_SPD_EEPROM
- SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
+#ifdef CONFIG_SYS_PCI1_MEM_PHYS
+ SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+ SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
#endif
- SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
+#ifdef CONFIG_SYS_PCI2_MEM_PHYS
SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
- SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1),
SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2),
- /* Map the whole localbus, including flash and reset latch. */
- SET_LAW(CONFIG_SYS_LBC_OPTION_BASE, LAWAR_SIZE_256M, LAW_TRGT_IF_LBC),
+#endif
+#ifdef CONFIG_SYS_RIO_MEM_PHYS
+ SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
+#endif
+ SET_LAW(CONFIG_SYS_LBC_OPTION_BASE, LAWAR_SIZE_256M, LAW_TRGT_IF_LBC)
};
int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/stxssa/tlb.c b/board/stx/common/tlb.c
similarity index 59%
rename from board/stxssa/tlb.c
rename to board/stx/common/tlb.c
index 0386432..6298eaa 100644
--- a/board/stxssa/tlb.c
+++ b/board/stx/common/tlb.c
@@ -1,9 +1,9 @@
/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, w...@denx.de.
*
+ * Copyright 2009 Alex Dubov <oa...@yahoo.com>
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
@@ -31,76 +31,90 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
/*
- * TLB 0: 64M Non-cacheable, guarded
- * 0xfc000000 6M4 FLASH
+ * TLB 0: 256M Non-cacheable, guarded
+ * 0xf0000000 256M LBC (FLASH included)
* Out of reset this entry is only 4K.
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
+ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_OPTION_BASE,
+ CONFIG_SYS_LBC_OPTION_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_64M, 1),
+ 0, 0, BOOKE_PAGESZ_256M, 1),
/*
- * TLB 1: 256M Non-cacheable, guarded
- * 0x80000000 256M PCI1 MEM First half
+ * TLB 1: 64M Non-cacheable, guarded
+ * 0xe000_0000 1M CCSRBAR
+ * 0xe200_0000 1M PCI1 IO
+ * 0xe210_0000 1M PCI2 IO
+ * 0xe300_0000 1M PCIe IO
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_256M, 1),
+ 0, 1, BOOKE_PAGESZ_64M, 1),
+#ifdef CONFIG_SYS_RIO_MEM_PHYS
/*
* TLB 2: 256M Non-cacheable, guarded
- * 0x90000000 256M PCI1 MEM Second half
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
+ SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT, CONFIG_SYS_RIO_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
/*
* TLB 3: 256M Non-cacheable, guarded
- * 0xa0000000 256M PCI2 MEM First half
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT + 0x10000000,
+ CONFIG_SYS_RIO_MEM_PHYS + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_256M, 1),
+#endif
+#ifdef CONFIG_SYS_PCI1_MEM_PHYS
/*
* TLB 4: 256M Non-cacheable, guarded
- * 0xb0000000 256M PCI2 MEM Second half
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000,
CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_256M, 1),
/*
- * TLB 5: 64M Non-cacheable, guarded
- * 0xe000_0000 1M CCSRBAR
- * 0xe200_0000 16M PCI1 IO
- * 0xe300_0000 16M PCI2 IO
+ * TLB 5: 256M Non-cacheable, guarded
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000,
+ CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_64M, 1),
+ 0, 5, BOOKE_PAGESZ_256M, 1),
+#endif
+#ifdef CONFIG_SYS_PCI2_MEM_PHYS
/*
* TLB 6: 256M Non-cacheable, guarded
- * 0xf0000000 Local bus expansion option.
- * 0xfb000000 Configuration Latch register (one word)
- * 0xfc000000 Up to 64M flash
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_LBC_OPTION_BASE, CONFIG_SYS_LBC_OPTION_BASE,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT, CONFIG_SYS_PCI2_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_256M, 1),
+
+ /*
+ * TLB 7: 256M Non-cacheable, guarded
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT + 0x10000000,
+ CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_256M, 1),
+#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/stxgp3/Makefile b/board/stx/stxgp3/Makefile
similarity index 95%
rename from board/stxgp3/Makefile
rename to board/stx/stxgp3/Makefile
index 5a68f11..dce320c 100644
--- a/board/stxgp3/Makefile
+++ b/board/stx/stxgp3/Makefile
@@ -26,10 +26,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS-y += $(BOARD).o
-COBJS-y += law.o
-COBJS-y += tlb.o
COBJS-y += flash.o
-COBJS-$(CONFIG_FSL_DDR1) += ddr.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
diff --git a/board/stxgp3/config.mk b/board/stx/stxgp3/config.mk
similarity index 100%
rename from board/stxgp3/config.mk
rename to board/stx/stxgp3/config.mk
diff --git a/board/stxgp3/flash.c b/board/stx/stxgp3/flash.c
similarity index 100%
rename from board/stxgp3/flash.c
rename to board/stx/stxgp3/flash.c
diff --git a/board/stxgp3/stxgp3.c b/board/stx/stxgp3/stxgp3.c
similarity index 100%
rename from board/stxgp3/stxgp3.c
rename to board/stx/stxgp3/stxgp3.c
diff --git a/board/stxgp3/u-boot.lds b/board/stx/stxgp3/u-boot.lds
similarity index 100%
rename from board/stxgp3/u-boot.lds
rename to board/stx/stxgp3/u-boot.lds
diff --git a/board/stxssa/Makefile b/board/stx/stxssa/Makefile
similarity index 95%
rename from board/stxssa/Makefile
rename to board/stx/stxssa/Makefile
index 9ab41ec..c0e9798 100644
--- a/board/stxssa/Makefile
+++ b/board/stx/stxssa/Makefile
@@ -26,9 +26,6 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS-y += $(BOARD).o
-COBJS-y += law.o
-COBJS-y += tlb.o
-COBJS-$(CONFIG_FSL_DDR1) += ddr.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
diff --git a/board/stxssa/config.mk b/board/stx/stxssa/config.mk
similarity index 100%
rename from board/stxssa/config.mk
rename to board/stx/stxssa/config.mk
diff --git a/board/stxssa/stxssa.c b/board/stx/stxssa/stxssa.c
similarity index 100%
rename from board/stxssa/stxssa.c
rename to board/stx/stxssa/stxssa.c
diff --git a/board/stxssa/u-boot.lds b/board/stx/stxssa/u-boot.lds
similarity index 100%
rename from board/stxssa/u-boot.lds
rename to board/stx/stxssa/u-boot.lds
diff --git a/board/stxxtc/Makefile b/board/stx/stxxtc/Makefile
similarity index 100%
rename from board/stxxtc/Makefile
rename to board/stx/stxxtc/Makefile
diff --git a/board/stxxtc/config.mk b/board/stx/stxxtc/config.mk
similarity index 100%
rename from board/stxxtc/config.mk
rename to board/stx/stxxtc/config.mk
diff --git a/board/stxxtc/stxxtc.c b/board/stx/stxxtc/stxxtc.c
similarity index 100%
rename from board/stxxtc/stxxtc.c
rename to board/stx/stxxtc/stxxtc.c
diff --git a/board/stxxtc/u-boot.lds b/board/stx/stxxtc/u-boot.lds
similarity index 100%
rename from board/stxxtc/u-boot.lds
rename to board/stx/stxxtc/u-boot.lds
diff --git a/board/stxxtc/u-boot.lds.debug b/board/stx/stxxtc/u-boot.lds.debug
similarity index 100%
rename from board/stxxtc/u-boot.lds.debug
rename to board/stx/stxxtc/u-boot.lds.debug
diff --git a/board/stxgp3/ddr.c b/board/stxgp3/ddr.c
deleted file mode 100644
index 93d1100..0000000
--- a/board/stxgp3/ddr.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- */
-
-#include <common.h>
-#include <i2c.h>
-
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
-
-static void
-get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address)
-{
- i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t));
-}
-
-
-unsigned int
-fsl_ddr_get_mem_data_rate(void)
-{
- return get_ddr_freq(0);
-}
-
-
-void
-fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd,
- unsigned int ctrl_num)
-{
- unsigned int i;
- unsigned int i2c_address = 0;
-
- for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
- if (ctrl_num == 0 && i == 0) {
- i2c_address = SPD_EEPROM_ADDRESS;
- }
- get_spd(&(ctrl_dimms_spd[i]), i2c_address);
- }
-}
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- /*
- * Factors to consider for CPO:
- * - frequency
- * - ddr1 vs. ddr2
- */
- popts->cpo_override = 0;
-
- /*
- * Factors to consider for write data delay:
- * - number of DIMMs
- *
- * 1 = 1/4 clock delay
- * 2 = 1/2 clock delay
- * 3 = 3/4 clock delay
- * 4 = 1 clock delay
- * 5 = 5/4 clock delay
- * 6 = 3/2 clock delay
- */
- popts->write_data_delay = 3;
-
- /* 2T timing enable */
- popts->twoT_en = 1;
-
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 0;
-}
diff --git a/board/stxgp3/law.c b/board/stxgp3/law.c
deleted file mode 100644
index ba89f0e..0000000
--- a/board/stxgp3/law.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, w...@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-/*
- * LAW(Local Access Window) configuration:
- *
- * 0x0000_0000 0x7fff_ffff DDR 2G
- * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
- * 0xc000_0000 0xdfff_ffff RapidIO 512M
- * 0xe000_0000 0xe000_ffff CCSR 1M
- * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
- * 0xf000_0000 0xf7ff_ffff SDRAM 128M
- * 0xfc00_0000 0xfc00_ffff Config Latch 64K
- * 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M
- *
- * Notes:
- * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
- * If flash is 8M at default position (last 8M), no LAW needed.
- */
-
-struct law_entry law_table[] = {
-#ifndef CONFIG_SPD_EEPROM
- SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
-#endif
- SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
- /* This is not so much the SDRAM map as it is the whole localbus map. */
- SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
- SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
- SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/stxgp3/tlb.c b/board/stxgp3/tlb.c
deleted file mode 100644
index aa11a5d..0000000
--- a/board/stxgp3/tlb.c
+++ /dev/null
@@ -1,130 +0,0 @@
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, w...@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /*
- * TLB 0: 16M Non-cacheable, guarded
- * 0xff000000 16M FLASH
- * Out of reset this entry is only 4K.
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_16M, 1),
-
- /*
- * TLB 1: 256M Non-cacheable, guarded
- * 0x80000000 256M PCI1 MEM First half
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_256M, 1),
-
- /*
- * TLB 2: 256M Non-cacheable, guarded
- * 0x90000000 256M PCI1 MEM Second half
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 2, BOOKE_PAGESZ_256M, 1),
-
- /*
- * TLB 3: 256M Non-cacheable, guarded
- * 0xc0000000 256M Rapid IO MEM First half
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_256M, 1),
-
- /*
- * TLB 4: 256M Non-cacheable, guarded
- * 0xd0000000 256M Rapid IO MEM Second half
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_256M, 1),
-
- /*
- * TLB 5: 64M Non-cacheable, guarded
- * 0xe000_0000 1M CCSRBAR
- * 0xe200_0000 16M PCI1 IO
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_64M, 1),
-
- /*
- * TLB 6: 64M Cacheable, non-guarded
- * 0xf000_0000 64M LBC SDRAM
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 6, BOOKE_PAGESZ_64M, 1),
-
- /*
- * TLB 7: 16K Non-cacheable, guarded
- * 0xfc000000 16K Configuration Latch register
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_LBC_LCLDEVS_BASE,
CONFIG_SYS_LBC_LCLDEVS_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 7, BOOKE_PAGESZ_16K, 1),
-
-#if !defined(CONFIG_SPD_EEPROM)
- /*
- * TLB 8, 9: 128M DDR
- * 0x00000000 64M DDR System memory
- * 0x04000000 64M DDR System memory
- * Without SPD EEPROM configured DDR, this must be setup manually.
- * Make sure the TLB count at the top of this table is correct.
- * Likely it needs to be increased by two for these entries.
- */
-#error("Update the number of table entries in tlb1_entry")
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 8, BOOKE_PAGESZ_64M, 1),
-
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000,
CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 9, BOOKE_PAGESZ_64M, 1),
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/cpu/mpc85xx/config.mk b/cpu/mpc85xx/config.mk
index 9e574a2..a7d948d 100644
--- a/cpu/mpc85xx/config.mk
+++ b/cpu/mpc85xx/config.mk
@@ -25,4 +25,4 @@ PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx -DCONFIG_E500 -ffixed-r2 \
-Wa,-me500 -msoft-float -mno-string
-PLATFORM_CPPFLAGS +=$(call cc-option,-mno-spe)
+PLATFORM_CPPFLAGS +=$(call cc-option,-mspe=no)
diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h
index 0424e29..12df277 100644
--- a/include/configs/stxgp3.h
+++ b/include/configs/stxgp3.h
@@ -78,6 +78,7 @@
*/
#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
#define CONFIG_SYS_LBC_SDRAM_SIZE 256 /* LBC SDRAM is 64MB
*/
+#define CONFIG_SYS_LBC_OPTION_BASE 0xf0000000
#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M
*/
#define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */
@@ -195,18 +196,20 @@
/* RapdIO Map configuration, mapped 1:1.
*/
-#define CONFIG_SYS_RIO_MEM_BASE 0xc0000000
-#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
-#define CONFIG_SYS_RIO_MEM_SIZE 0x200000000 /* 512 M */
+#define CONFIG_SYS_RIO_MEM_BASE 0xc0000000
+#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
+#define CONFIG_SYS_RIO_MEM_VIRT CONFIG_SYS_RIO_MEM_BASE
+#define CONFIG_SYS_RIO_MEM_SIZE 0x200000000 /* 512 M */
/* Standard 8560 PCI addressing, mapped 1:1.
*/
-#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
-#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCI1_IO_BASE 0xe2000000
-#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
-#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16 M */
+#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_VIRT CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCI1_IO_BASE 0xe2000000
+#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
+#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16 M */
#if defined(CONFIG_PCI) /* PCI Ethernet card */
diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h
index 2783f9e..1d2a52d 100644
--- a/include/configs/stxssa.h
+++ b/include/configs/stxssa.h
@@ -220,19 +220,21 @@
* Standard 8555 PCI mapping.
* Addresses are mapped 1-1.
*/
-#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
-#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
-#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */
-
-#define CONFIG_SYS_PCI2_MEM_BASE 0xa0000000
-#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
-#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI2_IO_PHYS 0xe3000000
-#define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */
+#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_VIRT CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
+#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */
+
+#define CONFIG_SYS_PCI2_MEM_BASE 0xa0000000
+#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
+#define CONFIG_SYS_PCI2_MEM_VIRT CONFIG_SYS_PCI2_MEM_BASE
+#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI2_IO_PHYS 0xe3000000
+#define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */
#if defined(CONFIG_PCI) /* PCI Ethernet card */
#define CONFIG_MPC85XX_PCI2 1
--
1.5.6.4
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