On Thu, 2015-11-05 at 08:23 +0000, Yuantian Tang wrote:
> Hi Jocke,
>
> we achieved deep sleep mode that did exactly what you asked for.
> If waken up from deep sleep, soc will resume from uboot and re-initialized
> DDR controller with contents
> untouched.
> Please refer to drivers/ddr/fsl/fsl_ddr_gen4.c and look at DEEP_SLEEP related
> code.
Looking at it now and it looks the same as for ddr3? Some questions though:
289 if (is_warm_boot()) {
289 /* enter self-refresh */
290 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2);
291 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
292 ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg);
Why do you need to force SR here? The DDR RAM must already be in SR at this
point?
I come from CPU reset state so my DDR controller has HW default values so
this does not feel safe.
293 /* do board specific memory setup */
294 board_mem_sleep_setup();
295
296 temp_sdram_cfg = (ddr_in32(&ddr->sdram_cfg) |
SDRAM_CFG_BI);
SDRAM_CFG_BI skips a lot(all?) init of DDR RAM. What if you want to change some
DDR RAM
timing/config due to a bug? Then you would have to force a cold start.
Do you use ECC? Seems to be some issues with ECC if you skip D_INIT
Jocke
>
> Regards,
> Yuantian
>
> > -----Original Message-----
> > From: Joakim Tjernlund [mailto:joakim.tjernl...@transmode.se]
> > Sent: Thursday, November 05, 2015 4:04 PM
> > To: Sun York-R58495 <york...@freescale.com>; u-boot@lists.denx.de
> > Cc: c...@cumulusnetworks.com; Sharma Bhupesh-B45370
> > <bhupesh.sha...@freescale.com>; tr...@konsulko.com;
> > l.majew...@samsung.com; Tang Yuantian-B29983
> > <yuantian.t...@freescale.com>; Kushwaha Prabhakar-B32579
> > <prabha...@freescale.com>; Liu Shengzhou-B36685
> > <shengzhou....@freescale.com>; yamad...@jp.panasonic.com
> > Subject: Re: [PATCH v1 0/7] Enable high speed and heavy load for DDR4 for
> > LSCH3
> >
> > On Wed, 2015-11-04 at 10:03 -0800, York Sun wrote:
> > > This patch set revises the DDR driver to support higher speed for DDR4
> > > under heavy load (two dual-rank DIMMs) for four-chipselect interleaving.
> > > Single quad-rank DIMM is not supported yet.
> >
> > Hi York
> >
> > Seeing these patches reminds me about something I have been mening to
> > ask, Is it possible init the ddr controller/ddr ram (using ECC also) but
> > still
> > retain (parts of) memory contents?
> >
> > I am looking at keeping data at the end of memory when performing a warm
> > start, but still init the controll/ddr ram (without D_INIT set).
> > This way one could pick up any changes to DDR timing if needed.
> > Before reboot, ddr ram is set to Self Refresh(SR).
> >
> > Jocke
_______________________________________________
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
