On Fri, 2015-11-06 at 02:24 +0000, Yuantian Tang wrote: > > > -----Original Message----- > > From: York Sun [mailto:york...@freescale.com] > > Sent: Friday, November 06, 2015 1:42 AM > > To: Joakim Tjernlund <joakim.tjernl...@transmode.se>; Tang Yuantian- > > B29983 <yuantian.t...@freescale.com>; u-boot@lists.denx.de > > Cc: Kushwaha Prabhakar-B32579 <prabha...@freescale.com>; Sharma > > Bhupesh-B45370 <bhupesh.sha...@freescale.com>; tr...@konsulko.com; > > Liu Shengzhou-B36685 <shengzhou....@freescale.com>; > > c...@cumulusnetworks.com; l.majew...@samsung.com; > > yamad...@jp.panasonic.com > > Subject: Re: [PATCH v1 0/7] Enable high speed and heavy load for DDR4 for > > LSCH3 > > > > > > > > On 11/05/2015 01:55 AM, Joakim Tjernlund wrote: > > > On Thu, 2015-11-05 at 08:23 +0000, Yuantian Tang wrote: > > > > Hi Jocke, > > > > > > > > we achieved deep sleep mode that did exactly what you asked for. > > > > If waken up from deep sleep, soc will resume from uboot and > > > > re-initialized DDR controller with contents untouched. > > > > Please refer to drivers/ddr/fsl/fsl_ddr_gen4.c and look at DEEP_SLEEP > > related code. > > > > > > Looking at it now and it looks the same as for ddr3? Some questions > > > though: > > > 289 if (is_warm_boot()) { > > > 289 /* enter self-refresh */ > > > 290 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2); > > > 291 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR; > > > 292 ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg); > > > > > > Why do you need to force SR here? The DDR RAM must already be in SR at > > this point? > > > I come from CPU reset state so my DDR controller has HW default values > > > so this does not feel safe. > > > > This may be redundant. If the code runs to this line, it should come back > > from > > a deep sleep. The core is in reset state but the DDR controller is not. It > > should > > be in self-refresh mode. I will leave that to Yuantian to comment. > > > This is mandatory. the steps are: re-enter SR mode, enable DDR controller, > exit SR mode. We do that to > smooth the transition and avoid any glitch caused when controller takes over > memory.
hmm, why not do this always? I can't hurt normal operation I think. It would be less special code for this type of operation. Jocke _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
