On Fri, Oct 23, 2015 at 10:47:28PM +0530, Jagan Teki wrote: > On 23 October 2015 at 02:55, Tom Rini <tr...@konsulko.com> wrote: > > On Thu, Oct 22, 2015 at 07:10:17PM -0200, Fabio Estevam wrote: > >> On Thu, Oct 22, 2015 at 6:50 PM, Jagan Teki <jt...@openedev.com> wrote: > >> > >> > reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK > >> > @@ -719,7 +719,7 @@ int cadence_qspi_apb_indirect_read_setup(struct > >> > cadence_spi_platdata *plat, > >> > #if defined(CONFIG_SPL_SPI_XIP) && defined(CONFIG_SPL_BUILD) > >> > writel(0x0, plat->regbase + CQSPI_REG_MODE_BIT); > >> > #else > >> > - writel(0xFF, plat->regbase + CQSPI_REG_MODE_BIT); > >> > + writel(GENMASK(7, 0), plat->regbase + > >> > CQSPI_REG_MODE_BIT); > >> > >> Is the 0xFF really a mask here? It seems it is just writing 0xFF to > >> the register directly without any masking operation. > > As register got initialized to all 1's like masking all to set may be > we can add a macro like MODE_BIT_MASK and then will assign GENMASK to > that.
Lets just leave it to 0xFF as I bet when you read the datasheet it says something along the lines of "write 0xFF first" or something like that. -- Tom
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