On Thu, Oct 22, 2015 at 6:50 PM, Jagan Teki <jt...@openedev.com> wrote:
> reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK > @@ -719,7 +719,7 @@ int cadence_qspi_apb_indirect_read_setup(struct > cadence_spi_platdata *plat, > #if defined(CONFIG_SPL_SPI_XIP) && defined(CONFIG_SPL_BUILD) > writel(0x0, plat->regbase + CQSPI_REG_MODE_BIT); > #else > - writel(0xFF, plat->regbase + CQSPI_REG_MODE_BIT); > + writel(GENMASK(7, 0), plat->regbase + CQSPI_REG_MODE_BIT); Is the 0xFF really a mask here? It seems it is just writing 0xFF to the register directly without any masking operation. _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
