On 23 October 2015 at 02:55, Tom Rini <tr...@konsulko.com> wrote: > On Thu, Oct 22, 2015 at 07:10:17PM -0200, Fabio Estevam wrote: >> On Thu, Oct 22, 2015 at 6:50 PM, Jagan Teki <jt...@openedev.com> wrote: >> >> > reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK >> > @@ -719,7 +719,7 @@ int cadence_qspi_apb_indirect_read_setup(struct >> > cadence_spi_platdata *plat, >> > #if defined(CONFIG_SPL_SPI_XIP) && defined(CONFIG_SPL_BUILD) >> > writel(0x0, plat->regbase + CQSPI_REG_MODE_BIT); >> > #else >> > - writel(0xFF, plat->regbase + CQSPI_REG_MODE_BIT); >> > + writel(GENMASK(7, 0), plat->regbase + CQSPI_REG_MODE_BIT); >> >> Is the 0xFF really a mask here? It seems it is just writing 0xFF to >> the register directly without any masking operation.
As register got initialized to all 1's like masking all to set may be we can add a macro like MODE_BIT_MASK and then will assign GENMASK to that. > > Indeed, with context on the #else side it looks like an old fashioned > "clear everything with magic value" which I suppose might technically be > the bitmask but it's not helping with clarity in this case. -- Jagan | openedev. _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
