On 08/20/2015 01:52 AM, Marcel Ziswiler wrote:
Enable early TPS6586X PMIC rail configuration setting SM0 being
VDD_CORE_1.2V to 1.2 volts and SM1 being VDD_CPU_1.0V to 1.0 volts.
While those are PMIC power-up defaults the SoC might have been reset
separately with certain rails being left at lower DVFS states which
is e.g. the case upon watchdog reset while otherwise nearly idling.
This fixes an issue being stuck in U-Boot's SPL upon watchdog reset
(e.g. running downstream L4T Linux kernel as there exists no mainline
Tegra20 watchdog driver as of yet).
Rather than enable this with yet another CONFIG_ option, perhaps we can
put this code into a C file dedicated to the colibri_t20 board, and then
have the common code call it (and implement a weak function that does
nothing to satisfy the linker on other boards).
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