On 08/20/2015 01:52 AM, Marcel Ziswiler wrote:
Implement early TPS6586X PMIC rail configuration setting SM0 being VDD_CORE_1.2V to 1.2 volts and SM1 being VDD_CPU_1.0V to 1.0 volts. While those are PMIC power-up defaults the SoC might have been reset separately with certain rails being left at lower DVFS states which is e.g. the case upon watchdog reset while otherwise nearly idling.
Is there any guarantee that the voltage levels are high enough for the AVP to run correctly before the CORE rail is adjusted? It sounds to me like a HW design issue; the SoC reset output should reset the PMIC too.
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