On 08/20/2015 01:52 AM, Marcel Ziswiler wrote:
Implement early TPS6586X PMIC rail configuration setting SM0 being
VDD_CORE_1.2V to 1.2 volts and SM1 being VDD_CPU_1.0V to 1.0 volts.
While those are PMIC power-up defaults the SoC might have been reset
separately with certain rails being left at lower DVFS states which
is e.g. the case upon watchdog reset while otherwise nearly idling.
diff --git a/arch/arm/mach-tegra/tegra20/cpu.c
b/arch/arm/mach-tegra/tegra20/cpu.c
static void enable_cpu_power_rail(void)
{
struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
u32 reg;
+ debug("%s entry\n", __func__);
+
+#ifdef CONFIG_TEGRA_EARLY_TPS6586X
+ tegra_i2c_ll_init();
+
+ /* Set SM0 being VDD_CORE_1.2V to 1.2 volts */
+ tegra_i2c_ll_write(TPS6586X_SM0V1_REG, 0x13);
Does the CORE rail get adjusted by DVFS? Hopefully if it does, it is
never set so low that AVP operation at reset is impossible...
+ udelay(1000);
all the delays in this patch seem very large. What drove the choice of
the delay values?
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