On Sunday, April 27, 2014 at 08:40:50 PM, Ian Campbell wrote:
> On Sat, 2014-04-26 at 20:27 +0200, Marek Vasut wrote:
> > This was a sheer luck this ever worked. Looking at the entire driver, to
> > fix all your issues with DMA and caches, it would be sufficient to
> > re-align "struct dw_eth_dev" properly.
> >
> > See drivers/net/designware.h:
> > 1) struct dmamacdescr {} is already __aligned(ARCH_DMA_MINALIGN)
> >
> > => This structure, if aligned in memory to proper boundary, can be
> > flushed/
> >
> > invalidated without problems.
> >
> > 2) struct dw_eth_dev {} can be aligned to ANY 4-byte boundary
> >
> > But this structure contains two arrays of struct dmamacdescr {} ,
> > which each have their elements' lenght aligned to ARCH_DMA_MINALIGN
> >
> > Solution:
> >
> > Your patch [1/3] and reorder the structure in designware.h so that the
> > struct dmamacdescr tx_mac_descrtable[]
> > struct dmamacdescr rx_mac_descrtable[]
> > are first and anything that does not need to be aligned follows. This
> > way, the DMA descriptors will always be aligned and you need not worry
> > about the flushes. You don't even need to ROUNDUP their length, since
> > they are already fine.
>
> That sounds like a good plan. I'll take a look.
>
> > When reordering the struct dw_eth_dev {}, make sure to add a comment
> > about the alignment.
>
> Of course.
Thanks
Best regards,
Marek Vasut
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