Dear Prabhakar Kushwaha, Prabhakar Kushwaha <prabhakar <at> freescale.com> writes:
> > > On 4/1/2014 4:40 AM, Rommel G Custodio wrote: > > Dear Prabhakar Kushwaha, > > > > Prabhakar Kushwaha <prabhakar <at> freescale.com> writes: > > 8>< snipped ><8 > >> +#Flush PBL data > >> +091380c0 000FFFFF > > That's a "Wait" command. > > Unless the "Flush" was command (that is in most PBI files I've read, > > Flush/Wait pait) was inadvertantly deleted. > > > > Flush command only work for CCSRBAR address space. It should not be used > for CPC-SRAM. > > This is the reason, it has been removed. Does this affect all mpc85xx cores? I've noticed this same weird behavior on a T1040QDS. A simple write to CPC-SRAM before a Flush command causes the LEDs to report an error. i.e 89ffff00 4bfff004 09138000 00000000 091380c0 00000001 After putting the CPC-SRAM write after the Flush the write was successful (as verified by a BDI-3000). i.e 09138000 00000000 091380c0 00000001 89ffff00 4bfff004 091380c0 00000001 BUT it seems this does not occur on the P5040DS. The P5040DS_SPIFLASH creates a u-boot that has Flush commands and it boots correctly. [local]$ xxd -g4 obj-P5040DS_SPIFLASH/u-boot.pbl : 00cc0a0: ffffffff 81ffffc0 ffffffff ffffffff ................ 00cc0b0: ffffffff ffffffff ffffffff ffffffff ................ 00cc0c0: ffffffff ffffffff ffffffff ffffffff ................ 00cc0d0: ffffffff ffffffff ffffffff ffffffff ................ 00cc0e0: ffffffff 4bfff004 09138000 00000000 ....K........... 00cc0f0: 091380c0 00000000 08138040 aa69eb89 ...........@.i.. On another note, if this affects all mpc85xx cores then I guess tools/pblimage.c needs updating. The add_end_cmd() always adds a Flush command prior to a CRC check (CONT=0) command. > > Regards, > Prabhakar > All the best, Rommel _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
