On Friday, February 07, 2014 at 05:24:27 PM, Stephen Warren wrote: > On 02/07/2014 06:48 AM, Marek Vasut wrote: > > On Friday, February 07, 2014 at 07:48:06 AM, Stephen Warren wrote: > >> On 02/06/2014 07:53 PM, Marek Vasut wrote: > >>> On Thursday, February 06, 2014 at 09:13:06 PM, Stephen Warren wrote: > >>>> From: Stephen Warren <swar...@nvidia.com> > >>>> > >>>> These data structures are passed to cache-flushing routines, and hence > >>>> must be conform to both the USB the cache-flusing alignment > >>>> requirements. That means aligning to USB_DMA_MINALIGN. This is > >>>> important on systems where cache lines are >32 bytes. > >>>> > >>>> Signed-off-by: Stephen Warren <swar...@nvidia.com> > >>> > >>> Acked-by: Marek Vasut <ma...@denx.de> > >> > >> Oh, I assumed you would be applying this? > > > > Yes I would , but the previous patch still needs some discussion. > > Oh OK. The patches don't depend on each-other in any way, so you can go > ahead and apply this now if you want. I should have actually sent them > separately rather than as a series.
Yeah, applied V2 of 1 and 2/2 now. Best regards, Marek Vasut _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
