From: Stephen Warren <swar...@nvidia.com>
These data structures are passed to cache-flushing routines, and hence
must be conform to both the USB the cache-flusing alignment requirements.
That means aligning to USB_DMA_MINALIGN. This is important on systems
where cache lines are >32 bytes.
Signed-off-by: Stephen Warren <swar...@nvidia.com>
---
drivers/usb/host/ehci-hcd.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 7068b762d8a4..6017090ebeec 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -1162,14 +1162,16 @@ create_int_queue(struct usb_device *dev, unsigned long
pipe, int queuesize,
debug("ehci intr queue: out of memory\n");
goto fail1;
}
- result->first = memalign(32, sizeof(struct QH) * queuesize);
+ result->first = memalign(USB_DMA_MINALIGN,
+ sizeof(struct QH) * queuesize);
if (!result->first) {
debug("ehci intr queue: out of memory\n");
goto fail2;
}
result->current = result->first;
result->last = result->first + queuesize - 1;
- result->tds = memalign(32, sizeof(struct qTD) * queuesize);
+ result->tds = memalign(USB_DMA_MINALIGN,
+ sizeof(struct qTD) * queuesize);
if (!result->tds) {
debug("ehci intr queue: out of memory\n");
goto fail3;
--
1.8.1.5
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