On 02/06/2014 07:53 PM, Marek Vasut wrote: > On Thursday, February 06, 2014 at 09:13:06 PM, Stephen Warren wrote: >> From: Stephen Warren <swar...@nvidia.com> >> >> These data structures are passed to cache-flushing routines, and hence >> must be conform to both the USB the cache-flusing alignment requirements. >> That means aligning to USB_DMA_MINALIGN. This is important on systems >> where cache lines are >32 bytes. >> >> Signed-off-by: Stephen Warren <swar...@nvidia.com> > > Acked-by: Marek Vasut <ma...@denx.de>
Oh, I assumed you would be applying this? _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
