From: Fabio Estevam <fabio.este...@freescale.com>
Since ROM may modify the LDO ramp up time according to fuse setting,
it is safer to reset the ramp up field to its default value of 00:
00: 64 cycles of 24MHz clock;
01: 128 cycles of 24MHz clock;
02: 256 cycles of 24MHz clock;
03: 512 cycles of 24MHz clock;
Signed-off-by: Anson Huang <b20...@freescale.com>
Signed-off-by: Jason Liu <r64...@freescale.com>
Signed-off-by: Fabio Estevam <fabio.este...@freescale.com>
---
Changes since v1:
- None
arch/arm/cpu/armv7/mx6/soc.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 6cbade7..13b9e36 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -93,6 +93,20 @@ void init_aips(void)
writel(0x00000000, &aips2->opacr4);
}
+static void clear_ldo_ramp(void)
+{
+ struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+ int reg;
+
+ /* ROM may modify LDO ramp up time according to fuse setting, so in
+ * order to be in the safe side we neeed to reset these settings to
+ * match the reset value: 0'b00
+ */
+ reg = readl(&anatop->ana_misc2);
+ reg &= ~(0x3f << 24);
+ writel(reg, &anatop->ana_misc2);
+}
+
/*
* Set the VDDSOC
*
@@ -113,6 +127,8 @@ static void set_vddsoc(u32 mv)
else
val = (mv - 700) / 25;
+ clear_ldo_ramp();
+
/*
* Mask out the REG_CORE[22:18] bits (REG2_TRIG)
* and set them to the calculated value (0.7V + val * 0.25V)
--
1.8.1.2
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