Malta boards may be used with cores which support L2 caches, however
U-boot does not yet support L2 cache for MIPS. Thus for the moment we'll
disable L2 caches by setting the L2B bit in Config2. This is specific to
MTI/Imagination MIPS cores which is why this is done for the Malta board
rather than generically.
Signed-off-by: Paul Burton <paul.bur...@imgtec.com>
---
board/malta/lowlevel_init.S | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/board/malta/lowlevel_init.S b/board/malta/lowlevel_init.S
index 1af34f1..ae09c27 100644
--- a/board/malta/lowlevel_init.S
+++ b/board/malta/lowlevel_init.S
@@ -12,6 +12,7 @@
#include <asm/addrspace.h>
#include <asm/regdef.h>
#include <asm/malta.h>
+#include <asm/mipsregs.h>
#ifdef CONFIG_SYS_BIG_ENDIAN
#define CPU_TO_GT32(_x) ((_x))
@@ -27,6 +28,12 @@
.globl lowlevel_init
lowlevel_init:
+ /* disable any L2 cache for now */
+ sync
+ mfc0 t0, CP0_CONFIG, 2
+ ori t0, t0, 0x1 << 12
+ mtc0 t0, CP0_CONFIG, 2
+
/* detect the core card */
li t0, KSEG1ADDR(MALTA_REVISION)
lw t0, 0(t0)
--
1.8.4
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