Add DT node for USB function.
Signed-off-by: Jim Lin <ji...@nvidia.com>
---
arch/arm/dts/tegra114.dtsi | 105 ++++++++++++++++++++++++++++++++
arch/arm/dts/tegra20.dtsi | 81 ++++++++++++++++++++++++
arch/arm/dts/tegra30.dtsi | 108 +++++++++++++++++++++++++++++++++
board/nvidia/dts/tegra114-dalmore.dts | 7 ++
board/nvidia/dts/tegra30-cardhu.dts | 6 ++
include/fdtdec.h | 2 +
lib/fdtdec.c | 2 +
7 files changed, 311 insertions(+), 0 deletions(-)
diff --git a/arch/arm/dts/tegra114.dtsi b/arch/arm/dts/tegra114.dtsi
index f86d18d..0f8387b 100644
--- a/arch/arm/dts/tegra114.dtsi
+++ b/arch/arm/dts/tegra114.dtsi
@@ -216,4 +216,109 @@
clocks = <&tegra_car 15>;
status = "disable";
};
+
+/* This table has USB timing parameters for each Oscillator frequency we
+ * support. There are four sets of values:
+ *
+ * 1. PLLU configuration information (reference clock is osc/clk_m and
+ * PLLU-FOs are fixed at 12MHz/60MHz/480MHz).
+ * Reference frequency MHZ 12.0 13.0 19.2 26.0
+ * ----------------------------------------------------
+ * DIVN 960 960 200 960
+ * DIVM 12 13 4 26
+ * CPCON 12 12 3 12
+ * LFCON 2 2 2 2
+ *
+ * 2. PLL CONFIGURATION & PARAMETERS for different clock generators:
+ * Reference frequency MHZ 12.0 13.0 19.2 26.0
+ * ----------------------------------------------------
+ * PLLU_ENABLE_DLY_COUNT 02 2 3 4
+ * PLLU_STABLE_COUNT 47 51 75 102
+ * PLL_ACTIVE_DLY_COUNT 08 9 12 9
+ * XTAL_FREQ_COUNT 118 127 188 254
+ *
+ * 3. Debounce values IdDig, Avalid, Bvalid, VbusValid, VbusWakeUp, and
+ * SessEnd. Each of these signals have their own debouncer and for each of
+ * those one out of two debouncing times can be chosen (BIAS_DEBOUNCE_A or
+ * BIAS_DEBOUNCE_B).
+ *
+ * The values of DEBOUNCE_A and DEBOUNCE_B are calculated as follows:
+ * 0xffff -> No debouncing at all
+ * <n> ms = <n> * 1000 / (1/19.2MHz) / 4
+ *
+ * So to program a 10 ms debounce for BIAS_DEBOUNCE_A, we have:
+ * BIAS_DEBOUNCE_A[15:0] = 10 * 1000 * 19.2 / 4 = 48000 = 0xBB80
+ *
+ * We need to use only DebounceA for BOOTROM. We don't need the DebounceB
+ * values, so we can keep those to default.
+ *
+ * 4. The 20 microsecond delay after bias cell operation.
+ * UTMIP_BIAS_PAD_TRK_COUNT
+ *
+ * enum {
+ * PARAM_DIVN, // PLL FEEDBACK DIVIDER
+ * PARAM_DIVM, // PLL INPUT DIVIDER
+ * PARAM_DIVP, // POST DIVIDER (2^N)
+ * PARAM_CPCON, // BASE PLLC CHARGE Pump setup ctrl
+ * PARAM_LFCON, // BASE PLLC LOOP FILter setup ctrl
+ * PARAM_ENABLE_DELAY_COUNT, // PLL-U Enable Delay Count
+ * PARAM_STABLE_COUNT, // PLL-U STABLE count
+ * PARAM_ACTIVE_DELAY_COUNT, // PLL-U Active delay count
+ * PARAM_XTAL_FREQ_COUNT, // PLL-U XTAL frequency count
+ * PARAM_DEBOUNCE_A_TIME, // 10MS DELAY for BIAS_DEBOUNCE_A
+ * PARAM_BIAS_TIME, // 20US DELAY AFter bias cell op
+ * // UTMIP_BIAS_PAD_TRK_COUNT
+ *};
+ */
+ usbparams@0 {
+ compatible = "nvidia,usbparams";
+ osc-frequency = <13000000>;
+ /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */
+ params = <0x3c0 0x0d 0x00 0xc 2 0x02 0x33 0x09 0x7f 0x7ef4 6>;
+ };
+
+ usbparams@1 {
+ compatible = "nvidia,usbparams";
+ osc-frequency = <19200000>;
+ params = <0x0c8 0x04 0x00 0x3 2 0x03 0x4b 0x0c 0xbc 0xbb80 8>;
+ };
+
+ usbparams@2 {
+ compatible = "nvidia,usbparams";
+ osc-frequency = <12000000>;
+ params = <0x3c0 0x0c 0x00 0xc 2 0x02 0x2f 0x08 0x76 0x7530 5>;
+ };
+
+ usbparams@3 {
+ compatible = "nvidia,usbparams";
+ osc-frequency = <26000000>;
+ params = <0x3c0 0x1a 0x00 0xc 2 0x04 0x66 0x09 0xfe 0xfde8
0xb>;
+ };
+
+ usb@7d000000 {
+ compatible = "nvidia,tegra30-ehci", "nvidia,tegra114-ehci";
+ reg = <0x7d000000 0x4000>;
+ interrupts = < 52 >;
+ phy_type = "utmi";
+ clocks = <&tegra_car 22>; /* PERIPH_ID_USBD */
+ status = "disabled";
+ };
+
+ usb@7d004000 {
+ compatible = "nvidia,tegra30-ehci", "nvidia,tegra114-ehci";
+ reg = <0x7d004000 0x4000>;
+ interrupts = < 53 >;
+ phy_type = "utmi";
+ clocks = <&tegra_car 58>; /* PERIPH_ID_USB2 */
+ status = "disabled";
+ };
+
+ usb@7d008000 {
+ compatible = "nvidia,tegra30-ehci", "nvidia,tegra114-ehci";
+ reg = <0x7d008000 0x4000>;
+ interrupts = < 129 >;
+ phy_type = "utmi";
+ clocks = <&tegra_car 59>; /* PERIPH_ID_USB3 */
+ status = "disabled";
+ };
};
diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi
index 3805750..d0e39b4 100644
--- a/arch/arm/dts/tegra20.dtsi
+++ b/arch/arm/dts/tegra20.dtsi
@@ -290,6 +290,87 @@
reg = <0x7000f400 0x200>;
};
+/* This table has USB timing parameters for each Oscillator frequency we
+ * support. There are four sets of values:
+ *
+ * 1. PLLU configuration information (reference clock is osc/clk_m and
+ * PLLU-FOs are fixed at 12MHz/60MHz/480MHz).
+ *
+ * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz
+ * ----------------------------------------------------------------------
+ * DIVN 960 (0x3c0) 200 (0c8) 960 (3c0h) 960 (3c0)
+ * DIVM 13 (0d) 4 (04) 12 (0c) 26 (1a)
+ * Filter frequency (MHz) 1 4.8 6 2
+ * CPCON 1100b 0011b 1100b 1100b
+ * LFCON0 0 0 0 0
+ *
+ * 2. PLL CONFIGURATION & PARAMETERS for different clock generators:
+ *
+ * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz
+ * ---------------------------------------------------------------------------
+ * PLLU_ENABLE_DLY_COUNT 02 (0x02) 03 (03) 02 (02) 04 (04)
+ * PLLU_STABLE_COUNT 51 (33) 75 (4B) 47 (2F) 102 (66)
+ * PLL_ACTIVE_DLY_COUNT 05 (05) 06 (06) 04 (04) 09 (09)
+ * XTAL_FREQ_COUNT 127 (7F) 187 (BB) 118 (76) 254 (FE)
+ *
+ * 3. Debounce values IdDig, Avalid, Bvalid, VbusValid, VbusWakeUp, and
+ * SessEnd. Each of these signals have their own debouncer and for each of
+ * those one out of two debouncing times can be chosen (BIAS_DEBOUNCE_A or
+ * BIAS_DEBOUNCE_B).
+ *
+ * The values of DEBOUNCE_A and DEBOUNCE_B are calculated as follows:
+ * 0xffff -> No debouncing at all
+ * <n> ms = <n> * 1000 / (1/19.2MHz) / 4
+ *
+ * So to program a 10 ms debounce for BIAS_DEBOUNCE_A, we have:
+ * BIAS_DEBOUNCE_A[15:0] = 10 * 1000 * 19.2 / 4 = 48000 = 0xBB80
+ *
+ * We need to use only DebounceA for BOOTROM. We don't need the DebounceB
+ * values, so we can keep those to default.
+ *
+ * 4. The 20 microsecond delay after bias cell operation.
+ * UTMIP_BIAS_PAD_TRK_COUNT
+ *
+ * enum {
+ * PARAM_DIVN, // PLL FEEDBACK DIVIDER
+ * PARAM_DIVM, // PLL INPUT DIVIDER
+ * PARAM_DIVP, // POST DIVIDER (2^N)
+ * PARAM_CPCON, // BASE PLLC CHARGE Pump setup ctrl
+ * PARAM_LFCON, // BASE PLLC LOOP FILter setup ctrl
+ * PARAM_ENABLE_DELAY_COUNT, // PLL-U Enable Delay Count
+ * PARAM_STABLE_COUNT, // PLL-U STABLE count
+ * PARAM_ACTIVE_DELAY_COUNT, // PLL-U Active delay count
+ * PARAM_XTAL_FREQ_COUNT, // PLL-U XTAL frequency count
+ * PARAM_DEBOUNCE_A_TIME, // 10MS DELAY for BIAS_DEBOUNCE_A
+ * PARAM_BIAS_TIME, // 20US DELAY AFter bias cell op
+ * // UTMIP_BIAS_PAD_TRK_COUNT
+ *};
+ */
+ usbparams@0 {
+ compatible = "nvidia,usbparams";
+ osc-frequency = <13000000>;
+ /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */
+ params = <0x3c0 0x0d 0x00 0xc 0 0x02 0x33 0x05 0x7f 0x7ef4 5>;
+ };
+
+ usbparams@1 {
+ compatible = "nvidia,usbparams";
+ osc-frequency = <19200000>;
+ params = <0x0c8 0x04 0x00 0x3 0 0x03 0x4b 0x06 0xbb 0xbb80 7>;
+ };
+
+ usbparams@2 {
+ compatible = "nvidia,usbparams";
+ osc-frequency = <12000000>;
+ params = <0x3c0 0x0c 0x00 0xc 0 0x02 0x2f 0x04 0x76 0x7530 5>;
+ };
+
+ usbparams@3 {
+ compatible = "nvidia,usbparams";
+ osc-frequency = <26000000>;
+ params = <0x3c0 0x1a 0x00 0xc 0 0x04 0x66 0x09 0xfe 0xfde8 9>;
+ };
+
usb@c5000000 {
compatible = "nvidia,tegra20-ehci", "usb-ehci";
reg = <0xc5000000 0x4000>;
diff --git a/arch/arm/dts/tegra30.dtsi b/arch/arm/dts/tegra30.dtsi
index ccf154f..3e6fbc4 100644
--- a/arch/arm/dts/tegra30.dtsi
+++ b/arch/arm/dts/tegra30.dtsi
@@ -216,4 +216,112 @@
clocks = <&tegra_car 15>;
status = "disabled";
};
+
+/* This table has USB timing parameters for each Oscillator frequency we
+ * support. There are four sets of values:
+ *
+ * 1. PLLU configuration information (reference clock is osc/clk_m and
+ * PLLU-FOs are fixed at 12MHz/60MHz/480MHz).
+ * (T3x)
+ * Reference frequency MHZ 12.0 13.0 19.2 26.0
+ * ----------------------------------------------------
+ * DIVN 960 960 200 960
+ * DIVM 12 13 4 26
+ * CPCON 12 12 3 12
+ * LFCON 1 1 0 1
+ *
+ * 2. PLL CONFIGURATION & PARAMETERS for different clock generators:
+ * (T3x)
+ * Reference frequency MHZ 12.0 13.0 19.2 26.0
+ * ----------------------------------------------------
+ * Index 8 0 4 12
+ * PLLU_ENABLE_DLY_COUNT 02 2 3 4
+ * PLLU_STABLE_COUNT 47 51 75 102
+ * PLL_ACTIVE_DLY_COUNT 08 9 12 9
+ * XTAL_FREQ_COUNT 118 127 188 254
+ *
+ * 3. Debounce values IdDig, Avalid, Bvalid, VbusValid, VbusWakeUp, and
+ * SessEnd. Each of these signals have their own debouncer and for each of
+ * those one out of two debouncing times can be chosen (BIAS_DEBOUNCE_A or
+ * BIAS_DEBOUNCE_B).
+ *
+ * The values of DEBOUNCE_A and DEBOUNCE_B are calculated as follows:
+ * 0xffff -> No debouncing at all
+ * <n> ms = <n> * 1000 / (1/19.2MHz) / 4
+ *
+ * So to program a 10 ms debounce for BIAS_DEBOUNCE_A, we have:
+ * BIAS_DEBOUNCE_A[15:0] = 10 * 1000 * 19.2 / 4 = 48000 = 0xBB80
+ *
+ * We need to use only DebounceA for BOOTROM. We don't need the DebounceB
+ * values, so we can keep those to default.
+ *
+ * 4. The 20 microsecond delay after bias cell operation.
+ * UTMIP_BIAS_PAD_TRK_COUNT
+ *
+ * enum {
+ * PARAM_DIVN, // PLL FEEDBACK DIVIDER
+ * PARAM_DIVM, // PLL INPUT DIVIDER
+ * PARAM_DIVP, // POST DIVIDER (2^N)
+ * PARAM_CPCON, // BASE PLLC CHARGE Pump setup ctrl
+ * PARAM_LFCON, // BASE PLLC LOOP FILter setup ctrl
+ * PARAM_ENABLE_DELAY_COUNT, // PLL-U Enable Delay Count
+ * PARAM_STABLE_COUNT, // PLL-U STABLE count
+ * PARAM_ACTIVE_DELAY_COUNT, // PLL-U Active delay count
+ * PARAM_XTAL_FREQ_COUNT, // PLL-U XTAL frequency count
+ * PARAM_DEBOUNCE_A_TIME, // 10MS DELAY for BIAS_DEBOUNCE_A
+ * PARAM_BIAS_TIME, // 20US DELAY After bias cell op
+ * // UTMIP_BIAS_PAD_TRK_COUNT
+ *};
+ */
+ usbparams@0 {
+ compatible = "nvidia,usbparams";
+ osc-frequency = <13000000>;
+ /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */
+ params = <0x3c0 0x0d 0x00 0xc 1 0x02 0x33 0x09 0x7f 0x7ef4 5>;
+ };
+
+ usbparams@1 {
+ compatible = "nvidia,usbparams";
+ osc-frequency = <19200000>;
+ params = <0x0c8 0x04 0x00 0x3 0 0x03 0x4b 0x0c 0xbc 0xbb80 7>;
+ };
+
+ usbparams@2 {
+ compatible = "nvidia,usbparams";
+ osc-frequency = <12000000>;
+ params = <0x3c0 0x0c 0x00 0xc 1 0x02 0x2f 0x08 0x76 0x7530 5>;
+ };
+
+ usbparams@3 {
+ compatible = "nvidia,usbparams";
+ osc-frequency = <26000000>;
+ params = <0x3c0 0x1a 0x00 0xc 1 0x04 0x66 0x09 0xfe 0xfde8 9>;
+ };
+
+ usb@7d000000 {
+ compatible = "nvidia,tegra30-ehci";
+ reg = <0x7d000000 0x4000>;
+ interrupts = < 52 >;
+ phy_type = "utmi";
+ clocks = <&tegra_car 22>; /* PERIPH_ID_USBD */
+ status = "disabled";
+ };
+
+ usb@7d004000 {
+ compatible = "nvidia,tegra30-ehci";
+ reg = <0x7d004000 0x4000>;
+ interrupts = < 53 >;
+ phy_type = "utmi";
+ clocks = <&tegra_car 58>; /* PERIPH_ID_USB2 */
+ status = "disabled";
+ };
+
+ usb@7d008000 {
+ compatible = "nvidia,tegra30-ehci";
+ reg = <0x7d008000 0x4000>;
+ interrupts = < 129 >;
+ phy_type = "utmi";
+ clocks = <&tegra_car 59>; /* PERIPH_ID_USB3 */
+ status = "disabled";
+ };
};
diff --git a/board/nvidia/dts/tegra114-dalmore.dts
b/board/nvidia/dts/tegra114-dalmore.dts
index 86e9459..435c01e 100644
--- a/board/nvidia/dts/tegra114-dalmore.dts
+++ b/board/nvidia/dts/tegra114-dalmore.dts
@@ -14,6 +14,7 @@
i2c4 = "/i2c@7000c700";
sdhci0 = "/sdhci@78000600";
sdhci1 = "/sdhci@78000400";
+ usb0 = "/usb@7d008000";
};
memory {
@@ -61,4 +62,10 @@
bus-width = <8>;
status = "okay";
};
+
+ usb@7d008000 {
+ /* SPDIF_IN: USB_VBUS_EN1 */
+ nvidia,vbus-gpio = <&gpio 86 0>;
+ status = "okay";
+ };
};
diff --git a/board/nvidia/dts/tegra30-cardhu.dts
b/board/nvidia/dts/tegra30-cardhu.dts
index 4d22b48..071a464 100644
--- a/board/nvidia/dts/tegra30-cardhu.dts
+++ b/board/nvidia/dts/tegra30-cardhu.dts
@@ -14,6 +14,7 @@
i2c4 = "/i2c@7000c700";
sdhci0 = "/sdhci@78000600";
sdhci1 = "/sdhci@78000000";
+ usb0 = "/usb@7d008000";
};
memory {
@@ -63,4 +64,9 @@
status = "okay";
bus-width = <8>;
};
+
+ usb@7d008000 {
+ nvidia,vbus-gpio = <&gpio 233 3>; /* PDD1, EN_3V3_PU */
+ status = "okay";
+ };
};
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 844991e..454c971 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -64,6 +64,8 @@ struct fdt_memory {
enum fdt_compat_id {
COMPAT_UNKNOWN,
COMPAT_NVIDIA_TEGRA20_USB, /* Tegra20 USB port */
+ COMPAT_NVIDIA_TEGRA30_USB, /* Tegra30 USB port */
+ COMPAT_NVIDIA_TEGRA114_USB, /* Tegra114 USB port */
COMPAT_NVIDIA_TEGRA114_I2C, /* Tegra114 I2C w/single clock source */
COMPAT_NVIDIA_TEGRA20_I2C, /* Tegra20 i2c */
COMPAT_NVIDIA_TEGRA20_DVC, /* Tegra20 dvc (really just i2c) */
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 403babd..fc18c4f 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -37,6 +37,8 @@ DECLARE_GLOBAL_DATA_PTR;
static const char * const compat_names[COMPAT_COUNT] = {
COMPAT(UNKNOWN, "<none>"),
COMPAT(NVIDIA_TEGRA20_USB, "nvidia,tegra20-ehci"),
+ COMPAT(NVIDIA_TEGRA30_USB, "nvidia,tegra30-ehci"),
+ COMPAT(NVIDIA_TEGRA114_USB, "nvidia,tegra114-ehci"),
COMPAT(NVIDIA_TEGRA114_I2C, "nvidia,tegra114-i2c"),
COMPAT(NVIDIA_TEGRA20_I2C, "nvidia,tegra20-i2c"),
COMPAT(NVIDIA_TEGRA20_DVC, "nvidia,tegra20-i2c-dvc"),
--
1.7.7
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