Lucas, On Tue, Dec 4, 2012 at 1:40 PM, Lucas Stach <d...@lynxeye.de> wrote: > Hi Tom, > > Am Dienstag, den 04.12.2012, 13:22 -0700 schrieb Tom Warren: > [...] >> >> > >> >> +#define V_NS16550_CLK 216000000 /* 216MHz >> >> (pllp_out0) */ >> > >> > I thought PLL_P ran at 408MHz on Tegra30? The kernel certainly sets it >> > up that way. >> >> See my previous reply. In the internal U-Boot repo I ported from, PLLP >> was initially set to 216MHz, then sped up to 408MHz. When this first >> round of patches is in, I can address going to 408MHz first thing. >> > Is running the PLL_P at 408MHz something which requires a lot of work? > If not, please do this and fold it into this patchset. It doesn't look > too nice adding things to upstream which have to be changed/removed > immediately after going in. > > Considering that Tegra 30 support is still not really in a usable state > after this patchset and the time left until things have to get ready for > the next merge window, I suppose you could do it the right way from the > start.
I'll investigate. Thanks, Tom > > Regards, > Lucas > _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
