Module Name: src
Committed By: skrll
Date: Wed Sep 18 08:31:50 UTC 2024
Modified Files:
src/sys/arch/riscv/starfive: jh7100_clkc.c jh7100_pinctrl.c
jh7110_clkc.c jh71x0_clkc.c jh71x0_usb.c
Log Message:
#define<space> consistency
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/starfive/jh7100_clkc.c \
src/sys/arch/riscv/starfive/jh71x0_clkc.c
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/riscv/starfive/jh7100_pinctrl.c \
src/sys/arch/riscv/starfive/jh7110_clkc.c \
src/sys/arch/riscv/starfive/jh71x0_usb.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/starfive/jh7100_clkc.c
diff -u src/sys/arch/riscv/starfive/jh7100_clkc.c:1.3 src/sys/arch/riscv/starfive/jh7100_clkc.c:1.4
--- src/sys/arch/riscv/starfive/jh7100_clkc.c:1.3 Sat Jul 27 07:09:50 2024
+++ src/sys/arch/riscv/starfive/jh7100_clkc.c Wed Sep 18 08:31:50 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: jh7100_clkc.c,v 1.3 2024/07/27 07:09:50 skrll Exp $ */
+/* $NetBSD: jh7100_clkc.c,v 1.4 2024/09/18 08:31:50 skrll Exp $ */
/*-
* Copyright (c) 2023 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: jh7100_clkc.c,v 1.3 2024/07/27 07:09:50 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: jh7100_clkc.c,v 1.4 2024/09/18 08:31:50 skrll Exp $");
#include <sys/param.h>
@@ -44,94 +44,94 @@ __KERNEL_RCSID(0, "$NetBSD: jh7100_clkc.
#include <riscv/starfive/jh71x0_clkc.h>
-#define JH7100_CLK_CPUNDBUS_ROOT 0
-#define JH7100_CLK_DSP_ROOT 2
-#define JH7100_CLK_GMACUSB_ROOT 3
-#define JH7100_CLK_PERH0_ROOT 4
-#define JH7100_CLK_PERH1_ROOT 5
-#define JH7100_CLK_VOUT_ROOT 7
-#define JH7100_CLK_AUDIO_ROOT 8
-#define JH7100_CLK_VOUTBUS_ROOT 11
-#define JH7100_CLK_CPUNBUS_ROOT_DIV 12
-#define JH7100_CLK_DSP_ROOT_DIV 13
-#define JH7100_CLK_PERH0_SRC 14
-#define JH7100_CLK_PERH1_SRC 15
-#define JH7100_CLK_PLL2_REF 19
-#define JH7100_CLK_CPU_CORE 20
-#define JH7100_CLK_CPU_AXI 21
-#define JH7100_CLK_AHB_BUS 22
-#define JH7100_CLK_APB1_BUS 23
-#define JH7100_CLK_APB2_BUS 24
-#define JH7100_CLK_DOM7AHB_BUS 26
-#define JH7100_CLK_SGDMA2P_AXI 31
-#define JH7100_CLK_SGDMA2P_AHB 33
-#define JH7100_CLK_VP6_CORE 38
-#define JH7100_CLK_JPEG_APB 50
-#define JH7100_CLK_SGDMA1P_BUS 84
-#define JH7100_CLK_SGDMA1P_AXI 85
-#define JH7100_CLK_AUDIO_DIV 95
-#define JH7100_CLK_AUDIO_SRC 96
-#define JH7100_CLK_AUDIO_12288 97
-#define JH7100_CLK_VOUT_SRC 109
-#define JH7100_CLK_DISPBUS_SRC 110
-#define JH7100_CLK_DISP_BUS 111
-#define JH7100_CLK_DISP_AXI 112
-#define JH7100_CLK_SDIO0_AHB 114
-#define JH7100_CLK_SDIO0_CCLKINT 115
-#define JH7100_CLK_SDIO0_CCLKINT_INV 116
-#define JH7100_CLK_SDIO1_AHB 117
-#define JH7100_CLK_SDIO1_CCLKINT 118
-#define JH7100_CLK_SDIO1_CCLKINT_INV 119
-#define JH7100_CLK_GMAC_AHB 120
-#define JH7100_CLK_GMAC_ROOT_DIV 121
-#define JH7100_CLK_GMAC_PTP_REF 122
-#define JH7100_CLK_GMAC_GTX 123
-#define JH7100_CLK_GMAC_RMII_TX 124
-#define JH7100_CLK_GMAC_RMII_RX 125
-#define JH7100_CLK_GMAC_TX 126
-#define JH7100_CLK_GMAC_TX_INV 127
-#define JH7100_CLK_GMAC_RX_PRE 128
-#define JH7100_CLK_GMAC_RX_INV 129
-#define JH7100_CLK_GMAC_RMII 130
-#define JH7100_CLK_GMAC_TOPHYREF 131
-#define JH7100_CLK_QSPI_AHB 137
-#define JH7100_CLK_SEC_AHB 140
-#define JH7100_CLK_TRNG_APB 144
-#define JH7100_CLK_OTP_APB 145
-#define JH7100_CLK_UART0_APB 146
-#define JH7100_CLK_UART0_CORE 147
-#define JH7100_CLK_UART1_APB 148
-#define JH7100_CLK_UART1_CORE 149
-#define JH7100_CLK_SPI0_APB 150
-#define JH7100_CLK_SPI0_CORE 151
-#define JH7100_CLK_SPI1_APB 152
-#define JH7100_CLK_SPI1_CORE 153
-#define JH7100_CLK_I2C0_APB 154
-#define JH7100_CLK_I2C0_CORE 155
-#define JH7100_CLK_I2C1_APB 156
-#define JH7100_CLK_I2C1_CORE 157
-#define JH7100_CLK_GPIO_APB 158
-#define JH7100_CLK_UART2_APB 159
-#define JH7100_CLK_UART2_CORE 160
-#define JH7100_CLK_UART3_APB 161
-#define JH7100_CLK_UART3_CORE 162
-#define JH7100_CLK_SPI2_APB 163
-#define JH7100_CLK_SPI2_CORE 164
-#define JH7100_CLK_SPI3_APB 165
-#define JH7100_CLK_SPI3_CORE 166
-#define JH7100_CLK_I2C2_APB 167
-#define JH7100_CLK_I2C2_CORE 168
-#define JH7100_CLK_I2C3_APB 169
-#define JH7100_CLK_I2C3_CORE 170
-#define JH7100_CLK_WDTIMER_APB 171
-#define JH7100_CLK_WDT_CORE 172
-#define JH7100_CLK_PWM_APB 181
-
-#define JH7100_CLK_PLL0_OUT 186
-#define JH7100_CLK_PLL1_OUT 187
-#define JH7100_CLK_PLL2_OUT 188
+#define JH7100_CLK_CPUNDBUS_ROOT 0
+#define JH7100_CLK_DSP_ROOT 2
+#define JH7100_CLK_GMACUSB_ROOT 3
+#define JH7100_CLK_PERH0_ROOT 4
+#define JH7100_CLK_PERH1_ROOT 5
+#define JH7100_CLK_VOUT_ROOT 7
+#define JH7100_CLK_AUDIO_ROOT 8
+#define JH7100_CLK_VOUTBUS_ROOT 11
+#define JH7100_CLK_CPUNBUS_ROOT_DIV 12
+#define JH7100_CLK_DSP_ROOT_DIV 13
+#define JH7100_CLK_PERH0_SRC 14
+#define JH7100_CLK_PERH1_SRC 15
+#define JH7100_CLK_PLL2_REF 19
+#define JH7100_CLK_CPU_CORE 20
+#define JH7100_CLK_CPU_AXI 21
+#define JH7100_CLK_AHB_BUS 22
+#define JH7100_CLK_APB1_BUS 23
+#define JH7100_CLK_APB2_BUS 24
+#define JH7100_CLK_DOM7AHB_BUS 26
+#define JH7100_CLK_SGDMA2P_AXI 31
+#define JH7100_CLK_SGDMA2P_AHB 33
+#define JH7100_CLK_VP6_CORE 38
+#define JH7100_CLK_JPEG_APB 50
+#define JH7100_CLK_SGDMA1P_BUS 84
+#define JH7100_CLK_SGDMA1P_AXI 85
+#define JH7100_CLK_AUDIO_DIV 95
+#define JH7100_CLK_AUDIO_SRC 96
+#define JH7100_CLK_AUDIO_12288 97
+#define JH7100_CLK_VOUT_SRC 109
+#define JH7100_CLK_DISPBUS_SRC 110
+#define JH7100_CLK_DISP_BUS 111
+#define JH7100_CLK_DISP_AXI 112
+#define JH7100_CLK_SDIO0_AHB 114
+#define JH7100_CLK_SDIO0_CCLKINT 115
+#define JH7100_CLK_SDIO0_CCLKINT_INV 116
+#define JH7100_CLK_SDIO1_AHB 117
+#define JH7100_CLK_SDIO1_CCLKINT 118
+#define JH7100_CLK_SDIO1_CCLKINT_INV 119
+#define JH7100_CLK_GMAC_AHB 120
+#define JH7100_CLK_GMAC_ROOT_DIV 121
+#define JH7100_CLK_GMAC_PTP_REF 122
+#define JH7100_CLK_GMAC_GTX 123
+#define JH7100_CLK_GMAC_RMII_TX 124
+#define JH7100_CLK_GMAC_RMII_RX 125
+#define JH7100_CLK_GMAC_TX 126
+#define JH7100_CLK_GMAC_TX_INV 127
+#define JH7100_CLK_GMAC_RX_PRE 128
+#define JH7100_CLK_GMAC_RX_INV 129
+#define JH7100_CLK_GMAC_RMII 130
+#define JH7100_CLK_GMAC_TOPHYREF 131
+#define JH7100_CLK_QSPI_AHB 137
+#define JH7100_CLK_SEC_AHB 140
+#define JH7100_CLK_TRNG_APB 144
+#define JH7100_CLK_OTP_APB 145
+#define JH7100_CLK_UART0_APB 146
+#define JH7100_CLK_UART0_CORE 147
+#define JH7100_CLK_UART1_APB 148
+#define JH7100_CLK_UART1_CORE 149
+#define JH7100_CLK_SPI0_APB 150
+#define JH7100_CLK_SPI0_CORE 151
+#define JH7100_CLK_SPI1_APB 152
+#define JH7100_CLK_SPI1_CORE 153
+#define JH7100_CLK_I2C0_APB 154
+#define JH7100_CLK_I2C0_CORE 155
+#define JH7100_CLK_I2C1_APB 156
+#define JH7100_CLK_I2C1_CORE 157
+#define JH7100_CLK_GPIO_APB 158
+#define JH7100_CLK_UART2_APB 159
+#define JH7100_CLK_UART2_CORE 160
+#define JH7100_CLK_UART3_APB 161
+#define JH7100_CLK_UART3_CORE 162
+#define JH7100_CLK_SPI2_APB 163
+#define JH7100_CLK_SPI2_CORE 164
+#define JH7100_CLK_SPI3_APB 165
+#define JH7100_CLK_SPI3_CORE 166
+#define JH7100_CLK_I2C2_APB 167
+#define JH7100_CLK_I2C2_CORE 168
+#define JH7100_CLK_I2C3_APB 169
+#define JH7100_CLK_I2C3_CORE 170
+#define JH7100_CLK_WDTIMER_APB 171
+#define JH7100_CLK_WDT_CORE 172
+#define JH7100_CLK_PWM_APB 181
+
+#define JH7100_CLK_PLL0_OUT 186
+#define JH7100_CLK_PLL1_OUT 187
+#define JH7100_CLK_PLL2_OUT 188
-#define JH7100_NCLKS 189
+#define JH7100_NCLKS 189
static const char *cpundbus_root_parents[] = {
Index: src/sys/arch/riscv/starfive/jh71x0_clkc.c
diff -u src/sys/arch/riscv/starfive/jh71x0_clkc.c:1.3 src/sys/arch/riscv/starfive/jh71x0_clkc.c:1.4
--- src/sys/arch/riscv/starfive/jh71x0_clkc.c:1.3 Mon Aug 19 07:33:55 2024
+++ src/sys/arch/riscv/starfive/jh71x0_clkc.c Wed Sep 18 08:31:50 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: jh71x0_clkc.c,v 1.3 2024/08/19 07:33:55 skrll Exp $ */
+/* $NetBSD: jh71x0_clkc.c,v 1.4 2024/09/18 08:31:50 skrll Exp $ */
/*-
* Copyright (c) 2023 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: jh71x0_clkc.c,v 1.3 2024/08/19 07:33:55 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: jh71x0_clkc.c,v 1.4 2024/09/18 08:31:50 skrll Exp $");
#include <sys/param.h>
@@ -43,9 +43,9 @@ __KERNEL_RCSID(0, "$NetBSD: jh71x0_clkc.
#include <riscv/starfive/jh71x0_clkc.h>
-#define RD4(sc, reg) \
+#define RD4(sc, reg) \
bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
-#define WR4(sc, reg, val) \
+#define WR4(sc, reg, val) \
bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
Index: src/sys/arch/riscv/starfive/jh7100_pinctrl.c
diff -u src/sys/arch/riscv/starfive/jh7100_pinctrl.c:1.2 src/sys/arch/riscv/starfive/jh7100_pinctrl.c:1.3
--- src/sys/arch/riscv/starfive/jh7100_pinctrl.c:1.2 Thu Feb 8 07:13:10 2024
+++ src/sys/arch/riscv/starfive/jh7100_pinctrl.c Wed Sep 18 08:31:50 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: jh7100_pinctrl.c,v 1.2 2024/02/08 07:13:10 skrll Exp $ */
+/* $NetBSD: jh7100_pinctrl.c,v 1.3 2024/09/18 08:31:50 skrll Exp $ */
/*-
* Copyright (c) 2023 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: jh7100_pinctrl.c,v 1.2 2024/02/08 07:13:10 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: jh7100_pinctrl.c,v 1.3 2024/09/18 08:31:50 skrll Exp $");
#include <sys/param.h>
@@ -55,9 +55,9 @@ struct jh7100_pinctrl_gpio_pin {
bool pin_actlo;
};
-#define GPIORD4(sc, reg) \
+#define GPIORD4(sc, reg) \
bus_space_read_4((sc)->sc_bst, (sc)->sc_gpio_bsh, (reg))
-#define GPIOWR4(sc, reg, val) \
+#define GPIOWR4(sc, reg, val) \
bus_space_write_4((sc)->sc_bst, (sc)->sc_gpio_bsh, (reg), (val))
#define GPIO_DIN(pin) (0x0048 + (((pin) / 32) * 4))
@@ -74,9 +74,9 @@ struct jh7100_pinctrl_gpio_pin {
#define GPI_NONE 0xff
-#define PCTLRD4(sc, reg) \
+#define PCTLRD4(sc, reg) \
bus_space_read_4((sc)->sc_bst, (sc)->sc_padctl_bsh, (reg))
-#define PCTLWR4(sc, reg, val) \
+#define PCTLWR4(sc, reg, val) \
bus_space_write_4((sc)->sc_bst, (sc)->sc_padctl_bsh, (reg), (val))
#define PAD_GPIO(pin) (0x0000 + (((pin) / 2) * 4))
Index: src/sys/arch/riscv/starfive/jh7110_clkc.c
diff -u src/sys/arch/riscv/starfive/jh7110_clkc.c:1.2 src/sys/arch/riscv/starfive/jh7110_clkc.c:1.3
--- src/sys/arch/riscv/starfive/jh7110_clkc.c:1.2 Mon Sep 9 07:34:08 2024
+++ src/sys/arch/riscv/starfive/jh7110_clkc.c Wed Sep 18 08:31:50 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: jh7110_clkc.c,v 1.2 2024/09/09 07:34:08 skrll Exp $ */
+/* $NetBSD: jh7110_clkc.c,v 1.3 2024/09/18 08:31:50 skrll Exp $ */
/*-
* Copyright (c) 2023 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: jh7110_clkc.c,v 1.2 2024/09/09 07:34:08 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: jh7110_clkc.c,v 1.3 2024/09/18 08:31:50 skrll Exp $");
#include <sys/param.h>
@@ -892,9 +892,9 @@ static const struct device_compatible_en
};
-#define RD4(sc, reg) \
+#define RD4(sc, reg) \
bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
-#define WR4(sc, reg, val) \
+#define WR4(sc, reg, val) \
bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
Index: src/sys/arch/riscv/starfive/jh71x0_usb.c
diff -u src/sys/arch/riscv/starfive/jh71x0_usb.c:1.2 src/sys/arch/riscv/starfive/jh71x0_usb.c:1.3
--- src/sys/arch/riscv/starfive/jh71x0_usb.c:1.2 Sun Aug 25 15:23:51 2024
+++ src/sys/arch/riscv/starfive/jh71x0_usb.c Wed Sep 18 08:31:50 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: jh71x0_usb.c,v 1.2 2024/08/25 15:23:51 skrll Exp $ */
+/* $NetBSD: jh71x0_usb.c,v 1.3 2024/09/18 08:31:50 skrll Exp $ */
/*-
* Copyright (c) 2023 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: jh71x0_usb.c,v 1.2 2024/08/25 15:23:51 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: jh71x0_usb.c,v 1.3 2024/09/18 08:31:50 skrll Exp $");
#include <sys/param.h>
@@ -49,9 +49,9 @@ struct jh71x0_usb_softc {
};
-#define RD4(sc, reg) \
+#define RD4(sc, reg) \
bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
-#define WR4(sc, reg, val) \
+#define WR4(sc, reg, val) \
bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
