Module Name: src Committed By: skrll Date: Tue Nov 12 07:21:42 UTC 2024
Modified Files:
src/sys/arch/riscv/starfive: jh7110_pciephy.c
Log Message:
Remove #if 0 / #endif blocks
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/starfive/jh7110_pciephy.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
