flight 119943 libvirt real [real]
http://logs.test-lab.xenproject.org/osstest/logs/119943/
Failures :-/ but no regressions.
Tests which did not succeed, but are not blocking:
test-armhf-armhf-libvirt-xsm 14 saverestore-support-checkfail like 119874
test-armhf-armhf-libvirt-raw 13 saveresto
On Fri, Feb 23, 2018 at 06:11:39PM +, Roger Pau Monné wrote:
>On Wed, Dec 06, 2017 at 03:50:14PM +0800, Chao Gao wrote:
>> Signed-off-by: Chao Gao
>> ---
>> xen/include/public/hvm/hvm_info_table.h | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/xen/include/public/
On Fri, Feb 23, 2018 at 04:42:10PM +, Roger Pau Monné wrote:
>On Wed, Dec 06, 2017 at 03:50:10PM +0800, Chao Gao wrote:
>> Intel SDM Extended XAPIC (X2APIC) -> "Initialization by System Software"
>> has the following description:
>>
>> "The ACPI interfaces for the x2APIC are described in Secti
On Mon, Feb 12, 2018 at 03:38:07PM +, Roger Pau Monné wrote:
>On Fri, Nov 17, 2017 at 02:22:28PM +0800, Chao Gao wrote:
>> ... handlding guest's invalidation request.
>>
>> To support pirq migration optimization and using VT-d posted interrupt to
>> inject msi from assigned devices, each time
... Sorry for the incomplete mail. I somehow hit the "send" button before I
finish composing the previous mail. And now it continues...
2018-02-24 10:50 GMT+08:00 Zhongze Liu :
> Hi Jan,
>
> (Last week was the Chinese Spring Festival, so I failed to follow up
> timely. Sorry for that.)
>
> 2018-02
On 4/28/16 12:40 PM, Wei Liu wrote:
> On Tue, Apr 26, 2016 at 09:38:45AM -0500, Doug Goldstein wrote:
>> When building debug use -Og as the optimization level if its available,
>> otherwise retain the use of -O0. -Og has been added by GCC to enable all
>> optimizations that to not affect debugging
On 2/22/18 11:12 PM, Tian, Kevin wrote:
>> From: Wei Liu
>> Sent: Thursday, February 22, 2018 5:47 AM
>>
>> Hi all
>>
>> At some point I would like to make CONFIG_HVM and CONFIG_PV work.
>> The
>> passthrough code is one of the road blocks for that work.
>
> Can you elaborate the motivation of thi
> From: Wei Liu [mailto:wei.l...@citrix.com]
> Sent: Saturday, February 24, 2018 12:08 AM
>
> On Fri, Feb 23, 2018 at 05:12:05AM +, Tian, Kevin wrote:
> > > From: Wei Liu
> > > Sent: Thursday, February 22, 2018 5:47 AM
> > >
> > > Hi all
> > >
> > > At some point I would like to make CONFIG_HV
> From: Jan Beulich [mailto:jbeul...@suse.com]
> Sent: Friday, February 23, 2018 4:37 PM
>
> ... for non-existent MSRs: wrmsr_hypervisor_regs()'s comment clearly
> says that the function returns 0 for unrecognized MSRs, so
> {svm,vmx}_msr_write_intercept() should not convert this into success. We
> From: Gao, Chao
> Sent: Saturday, February 24, 2018 9:51 AM
>
> On Mon, Feb 12, 2018 at 02:54:02PM +, Roger Pau Monné wrote:
> >On Fri, Nov 17, 2017 at 02:22:25PM +0800, Chao Gao wrote:
> >> When irq remapping is enabled, IOAPIC Redirection Entry may be in
> remapping
> >> format. If that, g
On Mon, Feb 12, 2018 at 03:16:25PM +, Roger Pau Monné wrote:
>On Fri, Nov 17, 2017 at 02:22:27PM +0800, Chao Gao wrote:
>> ... rather than a filtered one. Previously, some fields (reserved or
>> unalterable) are filtered by QEMU. These fields are useless for the
>> legacy interrupt format (i.e.
> From: Paul Durrant [mailto:paul.durr...@citrix.com]
> Sent: Friday, February 23, 2018 5:35 PM
>
> > -Original Message-
> > From: Tian, Kevin [mailto:kevin.t...@intel.com]
> > Sent: 23 February 2018 05:36
> > To: Paul Durrant ; xen-
> de...@lists.xenproject.org
> > Cc: Stefano Stabellini
> From: Paul Durrant [mailto:paul.durr...@citrix.com]
> Sent: Friday, February 23, 2018 5:41 PM
>
> > -Original Message-
> > From: Tian, Kevin [mailto:kevin.t...@intel.com]
> > Sent: 23 February 2018 05:17
> > To: Paul Durrant ; xen-
> de...@lists.xenproject.org
> > Cc: Stefano Stabellini
Hi Jan,
(Last week was the Chinese Spring Festival, so I failed to follow up
timely. Sorry for that.)
2018-02-15 16:58 GMT+08:00 Jan Beulich :
On 14.02.18 at 18:02, wrote:
>> 2018-02-14 16:37 GMT+08:00 Jan Beulich :
>> On 14.02.18 at 08:15, wrote:
2018-02-13 23:26 GMT+08:00 Jan Be
On Mon, Feb 12, 2018 at 02:54:02PM +, Roger Pau Monné wrote:
>On Fri, Nov 17, 2017 at 02:22:25PM +0800, Chao Gao wrote:
>> When irq remapping is enabled, IOAPIC Redirection Entry may be in remapping
>> format. If that, generate an irq_remapping_request and call the common
>
>"If that's the case
> From: Razvan Cojocaru [mailto:rcojoc...@bitdefender.com]
> Sent: Friday, February 23, 2018 3:32 PM
>
> On 02/23/2018 09:29 AM, Razvan Cojocaru wrote:
> > Lacking PCID support in the emulation layer creates two different way of
> > handling the NOFLUSH being set: one is in hardware, and this happ
flight 119921 xen-4.6-testing real [real]
http://logs.test-lab.xenproject.org/osstest/logs/119921/
Regressions :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
test-amd64-amd64-qemuu-nested-intel 17 debian-hvm-install/l1/l2 fail REGR. vs.
119227
Tests w
On Thu, 15 Feb 2018, Stefano Stabellini wrote:
> = AGL Whitepaper =
> Artem: please review the whitepaper, most of the content is already
> there.
> Everybody agrees that Xen Project should publish its own whitepaper.
>
> Certifications are mostly not about the code. Artem about to share an
> anal
On Fri, 23 Feb 2018, Julien Grall wrote:
> Hi all,
>
> Arm has recently published a SMC Calling Convention (SMCCC)
> specification update [1] that provides an optimised calling convention
> and optional, discoverable support for mitigating CVE-2017-5715 (XSA-254
> variant 2). ARM Trusted Firmware
> From: Roger Pau Monné [mailto:roger@citrix.com]
> Sent: Friday, February 23, 2018 6:18 PM
>
> On Fri, Feb 23, 2018 at 04:56:38AM +, Tian, Kevin wrote:
> > > From: Roger Pau Monne [mailto:roger@citrix.com]
> > > Sent: Tuesday, February 20, 2018 4:57 PM
> > >
> > > There a bunch of bit
On 02/22/2018 06:53 AM, Juergen Gross wrote:
When creating a pthread in xs_watch() try to get the minimal needed
size of the thread from glibc instead of using a constant. This avoids
problems when the library is used in programs with large per-thread
memory.
Use dlsym() to get the pointer to __
On Fri, 23 Feb 2018, Julien Grall wrote:
> Some PSCI functions are only available in the 32-bit version. After
> recent changes, Xen always needs to know whether the call was made using
> 32-bit id or 64-bit id. So we don't emulate reserved one.
>
> With the current naming scheme, it is not easy t
On Fri, 23 Feb 2018, Julien Grall wrote:
> Add the detection and runtime code for ARM_SMCCC_ARCH_WORKAROUND_1.
>
> Signed-off-by: Julien Grall
Reviewed-by: Stefano Stabellini
> ---
> Changes in v5:
> - Fold the fixup! patch which re-order registers into it.
>
> Changes in v4:
From this discussion:
https://www.spinics.net/lists/linux-mm/msg145604.html
I investigated whether it is feasible to re-enable deferred page
initialization on xen's para-vitalized domains. After studying the
code, I found non-intrusive way to do just that.
All we need to do is to assume that page
Juergen Gross noticed that commit
f7f99100d8d ("mm: stop zeroing memory during allocation in vmemmap")
broke XEN PV domains when deferred struct page initialization is enabled.
This is because the xen's PagePinned() flag is getting erased from struct
pages when they are initialized later in boot.
The maximum size for the input size was set to INPUT_SIZE, which is actually
the size of the data array inside the fuzz_corpus structure and so was not
abling user (or AFL) to fill in the whole structure. Changing to
sizeof(struct fuzz_corpus) correct this problem.
Signed-off-by: Paul Semel
---
flight 119894 qemu-mainline real [real]
http://logs.test-lab.xenproject.org/osstest/logs/119894/
Failures :-/ but no regressions.
Tests which did not succeed, but are not blocking:
test-armhf-armhf-libvirt-xsm 14 saverestore-support-checkfail like 119797
test-armhf-armhf-libvirt 14 sav
On 02/23/2018 05:30 PM, Wei Liu wrote:
On Fri, Feb 23, 2018 at 12:57:26AM +0100, Paul Semel wrote:
The minimum size for the input size was set to DATA_OFFSET + 1 which was meaning
that we were requesting at least one character of the data array to be filled.
This is not needed for the fuzzer t
On 02/24/2018 12:31 AM, Tamas K Lengyel wrote:
> On Fri, Feb 23, 2018 at 3:25 PM, Razvan Cojocaru
> wrote:
>> On 02/24/2018 12:06 AM, Tamas K Lengyel wrote:
>>> On Mon, Jan 8, 2018 at 5:49 AM, Alexandru Isaila
>>> wrote:
This patch is adding a way to enable/disable nested pagefault
even
On Fri, Feb 23, 2018 at 3:25 PM, Razvan Cojocaru
wrote:
> On 02/24/2018 12:06 AM, Tamas K Lengyel wrote:
>> On Mon, Jan 8, 2018 at 5:49 AM, Alexandru Isaila
>> wrote:
>>> This patch is adding a way to enable/disable nested pagefault
>>> events. It introduces the xc_monitor_nested_pagefault functi
On Fri, Feb 23, 2018 at 2:46 AM, Alexandru Isaila
wrote:
> At this moment the CPUID events for the AMD architecture are not
> forwarded to the monitor layer.
>
> This patch adds the CPUID event to the common capabilities and then
> forwards the event to the monitor layer.
>
> ---
> Changes sin
On 02/24/2018 12:06 AM, Tamas K Lengyel wrote:
> On Mon, Jan 8, 2018 at 5:49 AM, Alexandru Isaila
> wrote:
>> This patch is adding a way to enable/disable nested pagefault
>> events. It introduces the xc_monitor_nested_pagefault function
>> and adds the nested_pagefault_disabled in the monitor str
On Mon, Jan 8, 2018 at 5:49 AM, Alexandru Isaila
wrote:
> This patch is adding a way to enable/disable nested pagefault
> events. It introduces the xc_monitor_nested_pagefault function
> and adds the nested_pagefault_disabled in the monitor structure.
> This is needed by the introspection so it wi
flight 119891 linux-4.9 real [real]
http://logs.test-lab.xenproject.org/osstest/logs/119891/
Failures :-/ but no regressions.
Regressions which are regarded as allowable (not blocking):
test-armhf-armhf-xl-rtds 12 guest-start fail REGR. vs. 119562
Tests which did not succeed, b
On Fri, Feb 23, 2018 at 06:28:56PM +, Wei Liu wrote:
> On Fri, Feb 09, 2018 at 12:35:13PM +0100, Marek Marczykowski-Górecki wrote:
> > On Fri, Feb 09, 2018 at 11:03:55AM +, Roger Pau Monné wrote:
> > > Really adding Ian and Wei.
> > >
> > > On Fri, Feb 09, 2018 at 10:55:24AM +, Roger P
On Fri, Feb 23, 2018 at 06:47:57PM +, Wei Liu wrote:
> On Fri, Feb 09, 2018 at 12:14:03AM +0100, Marek Marczykowski-Górecki wrote:
> > When fd=-1, no savefile will be written, but the domain will still be
> > suspended (but not destroyed). The main reason for this functionality is
> > to suspen
Backend domain may be independently destroyed - there is no
synchronization of libxl structures (including /libxl tree) elsewhere.
Backend might also remove the device info from its backend xenstore
subtree on its own.
We have various cases (not comprehensive list):
- both frontend and backend o
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA256
Xen Security Advisory CVE-2017-5753,CVE-2017-5715,CVE-2017-5754 / XSA-254
version 12
Information leak via side effects of speculative execution
UPDATES IN VERSION 12
=
Corrections to AR
flight 119971 examine real [real]
http://logs.test-lab.xenproject.org/osstest/logs/119971/
Failures :-/ but no regressions.
Tests which did not succeed, but are not blocking:
examine-laxton1 2 hosts-allocate broken like 118286
examine-cubietruck-metzinger 2 hosts-all
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA256
Xen Security Advisory CVE-2017-5753,CVE-2017-5715,CVE-2017-5754 / XSA-254
version 11
Information leak via side effects of speculative execution
UPDATES IN VERSION 11
=
Information provi
Julien,
Looks good now
On 23.02.18 20:57, Julien Grall wrote:
Add the detection and runtime code for ARM_SMCCC_ARCH_WORKAROUND_1.
Signed-off-by: Julien Grall
Reviewed-by: Volodymyr Babchuk
---
Changes in v5:
- Fold the fixup! patch which re-order registers into it.
Cha
On Fri, Feb 23, 2018 at 01:27:43PM +, Roger Pau Monne wrote:
> Add a basic HPET functionality test, note that this test requires the
> HPET to support level triggered interrupts.
>
> Further improvements should add support for interrupt delivery, and
> testing all the available timers.
>
> Si
Thanks for your comment, Roger
I will try to polish this doc and resubmit.
(I put some comments below as well.)
On Fri, Feb 23, 2018 at 04:15:00PM +, Roger Pau Monné wrote:
> On Tue, Feb 13, 2018 at 05:50:01PM -0800, Dongwon Kim wrote:
> > Reference document for hyper_DMABUF driver
> >
> > Do
Signed-off-by: Julien Grall
Reviewed-by: Volodymyr Babchuk
Acked-by: Stefano Stabellini
---
Changes in v4:
- Add Stefano's acked-by
Changes in v2:
- Add Volodymyr's reviewed-by
---
xen/include/asm-arm/smccc.h | 16 ++--
1 file changed, 10 insertions(+), 6 d
PSCI 1.0 added the error return PSCI_INVALID_ADDRESS. It is used to
indicate the entry point address is known to be invalid.
In Xen case, this error could be returned when a 64-bit vCPU is using a
Thumb entry address.
For PSCI 0.1 implementation, return PSCI_INVALID_PARAMETERS instead.
Suggested
From the specification, the PSCI call MIGRATE_INFO_TYPE will return an
int32_t. Update the function return type to match it.
Signed-off-by: Julien Grall
Reviewed-by: Stefano Stabellini
Cc: mirela.simono...@aggios.com
---
Changes in v4:
- Add Stefano's reviewed-by
Changes in v3:
PSCI 1.0 and later allows the SMCCC version to be (indirectly) probed
via PSCI_FEATURES. If the PSCI_FEATURES does not exist (PSCI 0.2 or
earlier) and the function returns an error, then we assume SMCCC 1.0
is implemented.
Signed-off-by: Julien Grall
Reviewed-by: Stefano Stabellini
Reviewed-by:
The new SMC Calling Convention (v1.1) allows for a reduced overhead when
calling into the firmware, and provides a new feature discovery
mechanism. See "Firmware interfaces for mitigating CVE-2017-5715"
ARM DEN 00070A.
Signed-off-by: Julien Grall
Reviewed-by: Volodymyr Babchuk
Acked-by: Stefano
32-bit domain is able to select the instruction (ARM vs Thumb) to use
when boot a new vCPU via CPU_ON. This is indicated via bit[0] of the
entry point address (see "T32 support" in PSCI v1.1 DEN0022D). bit[0]
must be cleared when setting the PC.
At the moment, Xen is setting the CPSR.T but never c
Hi all,
Arm has recently published a SMC Calling Convention (SMCCC)
specification update [1] that provides an optimised calling convention
and optional, discoverable support for mitigating CVE-2017-5715 (XSA-254
variant 2). ARM Trusted Firmware (ATF) has already gained such an
implementation[2].
The function SMCCC_ARCH_WORKAROUND_1 will be called by the guest for
hardening the branch predictor. So we want the handling to be as fast as
possible.
As the mitigation is applied on every guest exit, we can check for the
call before saving all the context and return very early.
For now, only pr
Some PSCI functions are only available in the 32-bit version. After
recent changes, Xen always needs to know whether the call was made using
32-bit id or 64-bit id. So we don't emulate reserved one.
With the current naming scheme, it is not easy to know which call
supports 32-bit and 64-bit id. So
Add the detection and runtime code for ARM_SMCCC_ARCH_WORKAROUND_1.
Signed-off-by: Julien Grall
---
Changes in v5:
- Fold the fixup! patch which re-order registers into it.
Changes in v4:
- Re-order saving/restoring registers in
__smccc_workaround_1_smc_start
Xen is printing the same way the PSCI version for 0.1, 0.2 and later.
The only different is the former is hardcoded.
Furthermore PSCI is now used for other things than SMP bring up. So only
print the PSCI version in psci_init.
Signed-off-by: Julien Grall
Reviewed-by: Volodymyr Babchuk
Acked-by:
A bunch of PSCI functions are not prefixed with static despite no one is
using them outside the file and the prototype is not available in
psci.h.
Signed-off-by: Julien Grall
Reviewed-by: Volodymyr Babchuk
Acked-by: Stefano Stabellini
---
Changes in v4:
- Add Stefano's acked-by
Currently, the behavior of do_common_cpu will slightly change depending
on the PSCI version passed in parameter. Looking at the code, more the
specific 0.2 behavior could move out of the function or adapted for 0.1:
- x0/r0 can be updated on PSCI 0.1 because general purpose registers
are u
Add macros SMCCC_VERSION, SMCCC_VERSION_{MINOR, MAJOR} to easily convert
between a 32-bit value and a version number. The encoding is based on
2.2.2 in "Firmware interfaces for mitigation CVE-2017-5715" (ARM DEN 0070A).
Also re-use them to define ARM_SMCCC_VERSION_1_0 and ARM_SMCCC_VERSION_1_1.
S
Now that we've standardised on SMCCC v1.1 to perform the branch
prediction invalidation, let's drop the previous band-aid. If vendors
haven't updated their firmware to do SMCCC 1.1, they haven't updated
PSCI either, so we don't loose anything.
This is aligned with the Linux commit 3a0a397ff5ff.
S
This will make easier to know whether BP hardening has been enabled for
a CPU and which method is used.
Signed-off-by: Julien Grall
Reviewed-by: Volodymyr Babcuk
Acked-by: Stefano Stabellini
---
Changes in v4:
- Add Stefano's acked-by
Changes in v3:
- Add Volodymyr's r
One of the major improvement of SMCCC v1.1 is that it only clobbers the
first 4 registers, both on 32 and 64bit. This means that it becomes very
easy to provide an inline version of the SMC call primitive, and avoid
performing a function call to stash the registers that woudl otherwise
be clobbered
SMCCC 1.1 offers firmware-based CPU workarounds. In particular,
SMCCC_ARCH_WORKAROUND_1 provides BP hardening for variant 2 of XSA-254
(CVE-2017-5715).
If the hypervisor has some mitigation for this issue, report that we
deal with it using SMCCC_ARCH_WORKAROUND_1, as we apply the hypervisor
workar
At the moment, Xen provides virtual PSCI interface compliant with 0.1
and 0.2. Since them, the specification has been updated and the latest
version is 1.1 (see ARM DEN 0022D).
From an implementation point of view, only PSCI_FEATURES is mandatory.
The rest is optional and can be left unimplemented
On 23/02/18 18:18, Volodymyr Babchuk wrote:
Hi Julien,
Hi Volodymyr,
On 23.02.18 18:47, Julien Grall wrote:
Add the detection and runtime code for ARM_SMCCC_ARCH_WORKAROUND_1.
Signed-off-by: Julien Grall
---
Changes in v4:
- Re-order saving/restoring registers in
On Fri, Feb 23, 2018 at 05:41:48PM +0100, Dario Faggioli wrote:
> Make it possible to get and set a (Credit1) scheduler's
> vCPU migration delay via the SCHEDOP sysctl, from both
> libxl and xl (no change needed in libxc).
>
> Signed-off-by: Dario Faggioli
Acked-by: Wei Liu
___
On Fri, Feb 09, 2018 at 12:22:13AM +0100, Marek Marczykowski-Górecki wrote:
> Backend domain may be independently destroyed - there is no
> synchronization of libxl structures (including /libxl tree) elsewhere.
> Backend might also remove the device info from its backend xenstore
> subtree on its o
On Fri, Feb 09, 2018 at 12:14:03AM +0100, Marek Marczykowski-Górecki wrote:
> When fd=-1, no savefile will be written, but the domain will still be
> suspended (but not destroyed). The main reason for this functionality is
> to suspend the host while some domains are running, potentially holding
>
On Fri, Feb 09, 2018 at 12:35:13PM +0100, Marek Marczykowski-Górecki wrote:
> On Fri, Feb 09, 2018 at 11:03:55AM +, Roger Pau Monné wrote:
> > Really adding Ian and Wei.
> >
> > On Fri, Feb 09, 2018 at 10:55:24AM +, Roger Pau Monné wrote:
> > > So the problem is creation time for domains t
On Wed, Feb 07, 2018 at 08:04:10PM -0700, Jim Fehlig wrote:
> Applications like libvirt may not populate a device devid field,
> delegating that to libxl. If needed, the application can later
> retrieve the libxl-produced devid. Indeed most devices are handled
> this way in libvirt, channel devices
Hi Julien,
On 23.02.18 18:47, Julien Grall wrote:
Add the detection and runtime code for ARM_SMCCC_ARCH_WORKAROUND_1.
Signed-off-by: Julien Grall
---
Changes in v4:
- Re-order saving/restoring registers in
__smccc_workaround_1_smc_start
Looks like you missed to run --
On 23/02/18 18:02, Andre Przywara wrote:
Hi,
Hi Andre,
On 19/02/18 12:19, Julien Grall wrote:
Hi,
On 09/02/18 14:39, Andre Przywara wrote:
The VGIC supports virtual IRQs to be connected to a hardware IRQ, so
when a guest EOIs the virtual interrupt, it affects the state of that
correspond
On Wed, Dec 06, 2017 at 03:50:14PM +0800, Chao Gao wrote:
> Signed-off-by: Chao Gao
> ---
> xen/include/public/hvm/hvm_info_table.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/xen/include/public/hvm/hvm_info_table.h
> b/xen/include/public/hvm/hvm_info_table.h
> inde
On Fri, Feb 23, 2018 at 06:06:55PM +, Julien Grall wrote:
> Hi,
>
> On 23/02/18 18:05, Wei Liu wrote:
> > On Fri, Feb 23, 2018 at 05:46:39PM +, Julien Grall wrote:
> > >
> > >
> > > On 23/02/18 17:26, Wei Liu wrote:
> > > > On Wed, Feb 21, 2018 at 02:02:55PM +, Julien Grall wrote:
>
Hi,
On 23/02/18 18:05, Wei Liu wrote:
On Fri, Feb 23, 2018 at 05:46:39PM +, Julien Grall wrote:
On 23/02/18 17:26, Wei Liu wrote:
On Wed, Feb 21, 2018 at 02:02:55PM +, Julien Grall wrote:
A new helper copy_mfn_to_guest is introduced to easily to copy a MFN to
the guest memory.
Not
On Fri, Feb 23, 2018 at 05:46:39PM +, Julien Grall wrote:
>
>
> On 23/02/18 17:26, Wei Liu wrote:
> > On Wed, Feb 21, 2018 at 02:02:55PM +, Julien Grall wrote:
> > > A new helper copy_mfn_to_guest is introduced to easily to copy a MFN to
> > > the guest memory.
> > >
> > > Not functional
Hi,
On 19/02/18 12:19, Julien Grall wrote:
> Hi,
>
> On 09/02/18 14:39, Andre Przywara wrote:
>> The VGIC supports virtual IRQs to be connected to a hardware IRQ, so
>> when a guest EOIs the virtual interrupt, it affects the state of that
>> corresponding interrupt on the hardware side at the sam
On Mon, Jan 08, 2018 at 02:49:44PM +0200, Alexandru Isaila wrote:
> This patch is adding a way to enable/disable nested pagefault
> events. It introduces the xc_monitor_nested_pagefault function
> and adds the nested_pagefault_disabled in the monitor structure.
> This is needed by the introspection
On 23/02/18 17:26, Wei Liu wrote:
On Wed, Feb 21, 2018 at 02:02:55PM +, Julien Grall wrote:
A new helper copy_mfn_to_guest is introduced to easily to copy a MFN to
the guest memory.
Not functional change intended
Is there a reason to not make all guest accessors tyep-safe instead?
Cou
Hi Roger,
On 23/02/18 17:25, Roger Pau Monné wrote:
On Fri, Feb 23, 2018 at 04:02:17PM +, Julien Grall wrote:
Hi,
On 23/02/18 15:55, Jan Beulich wrote:
On 23.01.18 at 16:07, wrote:
diff --git a/xen/arch/arm/xen.lds.S b/xen/arch/arm/xen.lds.S
index c9b9546435..98b82680c6 100644
--- a/xen
On Tue, Feb 13, 2018 at 03:32:04PM +0200, Oleksandr Grytsov wrote:
> On Tue, Feb 13, 2018 at 2:06 PM, Wei Liu wrote:
>
> > On Tue, Feb 06, 2018 at 03:08:45PM +0200, Oleksandr Grytsov wrote:
> > > On Tue, Feb 6, 2018 at 2:36 PM, Wei Liu wrote:
> > >
> > > > On Thu, Dec 14, 2017 at 04:14:12PM +020
> -Original Message-
> From: Jan Beulich [mailto:jbeul...@suse.com]
> Sent: 23 February 2018 15:57
> To: Paul Durrant ; Roger Pau Monne
>
> Cc: Andrew Cooper ; xen-
> de...@lists.xenproject.org; Boris Ostrovsky ;
> Konrad Rzeszutek Wilk
> Subject: Re: [PATCH v8 03/11] x86/physdev: enable
On Fri, Feb 23, 2018 at 05:07:09PM +, Roger Pau Monné wrote:
> On Thu, Feb 22, 2018 at 02:20:12PM +0800, Chao Gao wrote:
> > On Fri, Feb 09, 2018 at 05:51:29PM +, Roger Pau Monné wrote:
> > >On Sat, Feb 10, 2018 at 01:21:09AM +0800, Chao Gao wrote:
> > >> On Fri, Feb 09, 2018 at 04:39:15PM
On Fri, Feb 23, 2018 at 05:16:57PM +, Colin King wrote:
> From: Colin Ian King
>
> The function xenvif_rx_skb is local to the source and does not need
> to be in global scope, so make it static.
>
> Cleans up sparse warning:
> drivers/net/xen-netback/rx.c:422:6: warning: symbol 'xenvif_rx_sk
On Wed, Feb 21, 2018 at 02:02:59PM +, Julien Grall wrote:
> Most of the users of page_to_mfn and mfn_to_page are either overriding
> the macros to make them work with mfn_t or use mfn_x/_mfn because the
> rest of the function use mfn_t.
>
> So make page_to_mfn and mfn_to_page return mfn_t by d
On Wed, Feb 21, 2018 at 02:02:57PM +, Julien Grall wrote:
> No functional change intended.
>
> Signed-off-by: Julien Grall
Reviewed-by: Wei Liu
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On Wed, Feb 21, 2018 at 02:02:56PM +, Julien Grall wrote:
> The current prototype is slightly confusing because it takes a guest
> physical address and a machine physical frame (not address!). Switching to
> MFN will improve safety and reduce the chance to mistakenly invert the
> 2 parameters.
>>> On 23.02.18 at 17:24, wrote:
> On 23/02/18 15:12, Jan Beulich wrote:
> On 23.02.18 at 15:03, wrote:
>>> On 13/02/18 14:37, Jan Beulich wrote:
>>> On 12.02.18 at 12:23, wrote:
> --- a/xen/include/asm-x86/alternative-asm.h
> +++ b/xen/include/asm-x86/alternative-asm.h
> @
On Wed, Feb 21, 2018 at 02:02:55PM +, Julien Grall wrote:
> A new helper copy_mfn_to_guest is introduced to easily to copy a MFN to
> the guest memory.
>
> Not functional change intended
Is there a reason to not make all guest accessors tyep-safe instead?
Wei.
__
flight 119966 xen-unstable-smoke real [real]
http://logs.test-lab.xenproject.org/osstest/logs/119966/
Failures :-/ but no regressions.
Tests which did not succeed, but are not blocking:
test-amd64-amd64-libvirt 13 migrate-support-checkfail never pass
test-arm64-arm64-xl-xsm 1
On Fri, Feb 23, 2018 at 04:02:17PM +, Julien Grall wrote:
> Hi,
>
> On 23/02/18 15:55, Jan Beulich wrote:
> > > > > On 23.01.18 at 16:07, wrote:
> > > diff --git a/xen/arch/arm/xen.lds.S b/xen/arch/arm/xen.lds.S
> > > index c9b9546435..98b82680c6 100644
> > > --- a/xen/arch/arm/xen.lds.S
> >
On Wed, Feb 21, 2018 at 02:02:53PM +, Julien Grall wrote:
> The current prototype is slightly confusing because it takes a virtual
> address and a physical frame (not address!). Switching to MFN will improve
> safety and reduce the chance to mistakenly invert the 2 parameters.
>
> Signed-off-b
On Wed, Feb 21, 2018 at 02:02:54PM +, Julien Grall wrote:
> No functional change intended.
>
> Signed-off-by: Julien Grall
Reviewed-by: Wei Liu
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On Fri, Feb 23, 2018 at 01:22:23PM +0800, Chao Gao wrote:
> On Mon, Feb 12, 2018 at 02:49:12PM +, Roger Pau Monné wrote:
> >On Fri, Nov 17, 2017 at 02:22:24PM +0800, Chao Gao wrote:
> >
> >> +struct hvm_hw_vvtd
> >> +{
> >> +uint32_t eim_enabled : 1,
> >> + intremap_enabled : 1;
On Fri, Feb 23, 2018 at 01:50:05AM -0700, Jan Beulich wrote:
> >>> On 22.02.18 at 19:46, wrote:
> > On Wed, Dec 06, 2017 at 03:50:14PM +0800, Chao Gao wrote:
> >> --- a/xen/include/public/hvm/hvm_info_table.h
> >> +++ b/xen/include/public/hvm/hvm_info_table.h
> >> @@ -32,7 +32,7 @@
> >> #define H
From: Colin Ian King
The function xenvif_rx_skb is local to the source and does not need
to be in global scope, so make it static.
Cleans up sparse warning:
drivers/net/xen-netback/rx.c:422:6: warning: symbol 'xenvif_rx_skb'
was not declared. Should it be static?
Signed-off-by: Colin Ian King
gas prior to binutils commit fbdf9406b0 (appears in 2.27) outputs symbol
table entries resulting from .file in reverse order. If we get two
consecutive file symbols, prefer the first one if that names an object
file or has a directory component (to cover multiply compiled files).
This is the same
On Thu, Feb 22, 2018 at 02:20:12PM +0800, Chao Gao wrote:
> On Fri, Feb 09, 2018 at 05:51:29PM +, Roger Pau Monné wrote:
> >On Sat, Feb 10, 2018 at 01:21:09AM +0800, Chao Gao wrote:
> >> On Fri, Feb 09, 2018 at 04:39:15PM +, Roger Pau Monné wrote:
> >> >On Fri, Nov 17, 2017 at 02:22:15PM +0
On Sun, Feb 11, 2018 at 01:31:41PM +0800, Chao Gao wrote:
> On Fri, Feb 09, 2018 at 05:44:17PM +, Roger Pau Monné wrote:
> >On Fri, Nov 17, 2017 at 02:22:18PM +0800, Chao Gao wrote:
> >> +static int vvtd_delivery(struct domain *d, uint8_t vector,
> >> + uint32_t dest, bo
flight 119884 seabios real [real]
http://logs.test-lab.xenproject.org/osstest/logs/119884/
Regressions :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
test-amd64-amd64-xl-qemuu-ws16-amd64 17 guest-stop fail REGR. vs. 115539
Tests which did not suc
SMCCC 1.1 offers firmware-based CPU workarounds. In particular,
SMCCC_ARCH_WORKAROUND_1 provides BP hardening for variant 2 of XSA-254
(CVE-2017-5715).
If the hypervisor has some mitigation for this issue, report that we
deal with it using SMCCC_ARCH_WORKAROUND_1, as we apply the hypervisor
workar
---
xen/arch/arm/arm64/bpi.S | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/xen/arch/arm/arm64/bpi.S b/xen/arch/arm/arm64/bpi.S
index 981fb83a88..b59e307b0f 100644
--- a/xen/arch/arm/arm64/bpi.S
+++ b/xen/arch/arm/arm64/bpi.S
@@ -85,8 +85,8 @@ ENTRY(__psci_hyp_bp_inval_end)
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