This will make easier to know whether BP hardening has been enabled for
a CPU and which method is used.
Signed-off-by: Julien Grall <julien.gr...@arm.com>
Reviewed-by: Volodymyr Babcuk <volodymyr_babc...@epam.com>
Acked-by: Stefano Stabellini <sstabell...@kernel.org>
---
Changes in v4:
- Add Stefano's acked-by
Changes in v3:
- Add Volodymyr's reviewed-by
Changes in v2:
- Patch added
---
xen/arch/arm/cpuerrata.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/xen/arch/arm/cpuerrata.c b/xen/arch/arm/cpuerrata.c
index c243521ed4..8d5f8d372a 100644
--- a/xen/arch/arm/cpuerrata.c
+++ b/xen/arch/arm/cpuerrata.c
@@ -79,7 +79,8 @@ static bool copy_hyp_vect_bpi(unsigned int slot, const char
*hyp_vec_start,
static bool __maybe_unused
install_bp_hardening_vec(const struct arm_cpu_capabilities *entry,
const char *hyp_vec_start,
- const char *hyp_vec_end)
+ const char *hyp_vec_end,
+ const char *desc)
{
static int last_slot = -1;
static DEFINE_SPINLOCK(bp_lock);
@@ -94,6 +95,9 @@ install_bp_hardening_vec(const struct arm_cpu_capabilities
*entry,
if ( !entry->matches(entry) )
return true;
+ printk(XENLOG_INFO "CPU%u will %s on exception entry\n",
+ smp_processor_id(), desc);
+
/*
* No need to install hardened vector when the processor has
* ID_AA64PRF0_EL1.CSV2 set.
@@ -157,7 +161,8 @@ static int enable_psci_bp_hardening(void *data)
*/
if ( psci_ver >= PSCI_VERSION(0, 2) )
ret = install_bp_hardening_vec(data, __psci_hyp_bp_inval_start,
- __psci_hyp_bp_inval_end);
+ __psci_hyp_bp_inval_end,
+ "call PSCI get version");
else if ( !warned )
{
ASSERT(system_state < SYS_STATE_active);
--
2.11.0
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