[USRP-users] Error creating RFNoC FPGA image with OOT module

We are currently getting an error attempting to build a fpga image when running the following which points to the OOT module using the -I option ./uhd_image_builder.py twochannelsiggen duc fft -I /home/joseavila/Documents/gnuradio_source/rfnoc-siggen2ch/rfnoc/fpga-src/ -d x310 -t X310_RFNOC_H

[USRP-users] Error in RFNoC grc with OOT module

Hello we are developing an OOT module following the tutorial, but similar to siggen, but are currently encountering an error that comes up with ./testtwochannel.py The error that comes up is the following File "./testtwochannel.py", line 97 self.siggen2ch_twochannelsiggen_0 = Template er

Re: [USRP-users] Error in RFNoC grc with OOT module

ted, it is always recommended to update. Regards, -N On Wed, Oct 4, 2017 at 11:02 PM, Avila, Jose A via USRP-users mailto:usrp-users@lists.ettus.com>> wrote: Hello we are developing an OOT module following the tutorial, but similar to siggen, but are currently encountering an error th

Re: [USRP-users] Error creating RFNoC FPGA image with OOT module

pga-src', '')) As said, this fix will be pushed soon, but for now you can avoid problems by doing it manually. Regards, - Nicolas On Tue, Oct 3, 2017 at 9:21 PM, Avila, Jose A via USRP-users mailto:usrp-users@lists.ettus.com>> wrote: We are currently getting an e

[USRP-users] RFNoC OOT Module Error with FPGA Image

Hello we are getting the following error when probing the FPGA in X310 after installing the created bit file. Error:Runtime error: Cannot get() on an uninitialized (empty) property. The testbench runs successfully but after creating the bit file and uploading it into the SDR we get the error

Re: [USRP-users] RFNoC OOT Module Error with FPGA Image

$ROOTDIR/rfnoc/blocks/$MODULE_NAME.xml file. You may be reading a value before it has been initialized, look at arguments section and make sure you are not reading a value before it has been written. Good luck. On Tue, Nov 28, 2017 at 3:59 PM, Avila, Jose A via USRP-users mailto:usrp-users

[USRP-users] N310 FPGA image mismatch with UHD

Hello, I created an image for the N310 with the fpga master branch commit 615d9b8eeb94ee2d19c3b1e7aa526d4999495e05. I have UHD installed master branch commit 3b42e6f029f0d3de0f54d720964357aa0a32986f. When I go to probe the N310 I get the following error [ERROR] [0/DmaFIFO_0] Major compat n

[USRP-users] 4 channels tx on N310

Hello, We are trying to transmit out of the N310 with 4 channels simultaneously, with the attached flowgraph we got it to transmit by using 2 rfnoc:radio blocks with 2 channels each but we can't seem to find where to change the center frequency of the 2nd channel of the rfnoc: radio block. T