The errors about locked IP usually means the Vivado version doesn't match.
But you say it reports 2021.1_AR76780, which seems correct. Running "make
cleanall" (cleanall is one word in this case) should clean out any stale
files that may have been generated with the wrong version. Just to be sure,
m
Vivado is not installed on the machine connected to the X410, let's called it
SYS_A. SYS_A has UHD 4.4 installed.
SYS_B has both Vivado and UHD 4.4 installed. The OOT block is created, added to
x410_rfnoc_image_core.yml and build on SYS_B.
Besides the bit file, what other files need to be copie
Hello Wade,
if this is an indicator for a version mismatch, am I using the wrong version of
UHD? I cloned this branch: https://github.com/EttusResearch/uhd/tree/UHD-4.3
(commit 1f8fd3457 uhd: Prepare branch for 4.3.0.0 release)
To make sure that we’re on the same page, I reset my repo clone to t
Hello everyone,
*Presentation*: I'm trying to use the URSP E312 to do real-time
acquisition/processing of LTE signals in the PL part.
*Software: *
* - *Vivado 2023.1
- Vitis 2023.1
- Ubuntu 20.04 / Kernel: 5.10.102.1
- hdl master branch https://github.com/
Hey all,
trying to send a text file using B200 and receive it using B210 or PLUTO
over OFDM Tx/Rx blocks.
the setup works fine, but I need this setup to be repeated for 100
different text files. So, I modified the python code to read, send and
transmit the files one by one. the code works good for
On 13/07/2023 12:04, Moath Sulaiman via USRP-users wrote:
Hey all,
trying to send a text file using B200 and receive it using B210 or
PLUTO over OFDM Tx/Rx blocks.
the setup works fine, but I need this setup to be repeated for 100
different text files. So, I modified the python code to read, se
Hi all,
I have a USRP where I have a problem accessing the FPGA to program it.
Normally we use image loader like so:
uhd_image_loader --args="type=x300,addr=192.168.40.2"
--fpga-path="AnFpgaImage.bit"
If I bring up enp1s0f0 like so:
sudo ifconfig enp1s0f0 192.168.40.1 netmask 255.255.255.0
Onc
That UHD-4.3 branch should work. You could try 4.4 but 4.3 used the same
Vivado version.
Just to be clear we're using the same process, here's how I would start the
build:
git clone https://github.com/EttusResearch/uhd
git checkout UHD-4.3
cd ./uhd/fpga/usrp3/top/n3xx
source setupenv.sh
make N310
On 13/07/2023 13:20, cyberphox wrote:
Hi all,
I have a USRP where I have a problem accessing the FPGA to program
it. Normally we use image loader like so:
uhd_image_loader --args="type=x300,addr=192.168.40.2"
--fpga-path="AnFpgaImage.bit"
If I bring up enp1s0f0 like so:
sudo ifconfig enp1s
Hi Marcus,
We are doing this from the embedded host PC, not from the 10G connection
externally
Thank you
On Thu, 13 Jul 2023 at 19:17, Marcus D. Leech
wrote:
> On 13/07/2023 13:20, cyberphox wrote:
>
> Hi all,
>
> I have a USRP where I have a problem accessing the FPGA to program it.
> Normal
I am trying to understand the OTW formats available on the X310. Does it
support signed complex 8-bit sampling (sc8 wire format) for a receive stream? I
am reading forum/listserv posts from ~2018 saying X310 does not support it on
account of the 10Gig link being enough to stream at 200Msps @ 16
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