Hello everyone,
*Presentation*: I'm trying to use the URSP E312 to do real-time
acquisition/processing of LTE signals in the PL part.
*Software: *
* - *Vivado 2023.1
- Vitis 2023.1
- Ubuntu 20.04 / Kernel: 5.10.102.1
- hdl master branch https://github.com/analogdevicesinc/hdl
*BUILD: *https://wiki.analog.com/resources/fpga/docs/build
- no-OS master branch
https://github.com/analogdevicesinc/no-OS *BUILD*:
https://wiki.analog.com/resources/no-os/build
*Problem: *Using these codes, I had a problem initializing the AD9361
without touching the code. Here's what I had in the serial port:
/ cf-ad9361-lpc: Status errors//
// SAMPL CLK: 61440000 tuning: RX//
// 0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f://
// 0:# # # # # # # # # # # # # # # #//
// 1:# # # # # # # # # # # # # # # #//
// ad9361_dig_tune_delay: Tuning RX FAILED/
So I made a post on ADI Engineer Zone:
https://ez.analog.com/microcontroller-no-os-drivers/f/q-a/571320/usrp-e312-ad9361---ad9361_dig_tune_delay-tuning-rx-failed
And someone suggested this commit to solve the problem:
https://github.com/analogdevicesinc/no-OS/compare/master...usrp_e310_work/
/
I now have on the serial port:
cf-ad9361-lpc: Successfully initialized (61439514 Hz)
ad9361_init : AD936x Rev 2 successfully initialized
Sampling frequency is: 30720000
New sampling frequency is: 15360000
LO frequency of TX is: 90000000
cf-ad9361-dds-core-lpc: Successfully initialized (30718994 Hz)
DMA_EXAMPLE: address=0x141050 samples=65536 channels=4 bits=16
Done
I still don't see any output signals on TX when using a high-frequency
oscilloscope.
How do I fix this?
Do you need further informations?
Are there any other code possibilities for embedded LTE signal
processing on the PL part?
Thank you very much for your help.
Regards,
Rémi LETELLIER
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