[USRP-users] uhd and srsLTE do not want to join together :)

Hi, I asked this already in the srslte list, with no success. Uhd built fine and works.And I want to add, the mentioned setup runs in my VM just fine, so maybe some missing prerequisite the is not mentioned in the documents? I updated an old Ubuntu 12.04 setup in steps to 18.04, headless i7 mach

[USRP-users] B210 on windows - FPGA compatibility issue - help pls

Hi all, trying to run B210 in a Win7 32bit but getting the error message below: UHD:Status> Exception 05A0 (1440), RuntimeError: Expected FPGA compatibility number 14, but got 13:The FPGA build is not compatible with the host code build. Tried to switch between few FPGA images and Firmwar

Re: [USRP-users] uhd and srsLTE do not want to join together :)

The API was changed in the master branch of UHD. You need to build a release of UHD. I've successfully built srsLTE with the v3.13.0.3-rc1 release. git checkout v3.13.0.3-rc1 Ron On 1/28/19 03:28, Ralph A. Schmid, dk5ras via USRP-users wrote: Hi, I asked this already in the srslte list, wit

Re: [USRP-users] B210 on windows - FPGA compatibility issue - help pls

This sounds like your FPGA image repository is out of date with respect to your UHD build. Have you run uhd_images_downloader? Sent from my iPhone > On Jan 28, 2019, at 7:25 AM, Eduardo Erlemann via USRP-users > wrote: > > Hi all, trying to run B210 in a Win7 32bit but getting the error mes

[USRP-users] Live rate changes within an RFNOC block

I have an RFNOC block that, based on a control register can either decimate the signal it's working on or leave the output rate the same as the input rate. If I set the control register to an initial value (either decimate, or not decimate) and let the system run, it works fine in either mode. If I

Re: [USRP-users] Live rate changes within an RFNOC block

Hi Andrew, This is an issue we are aware of related to the RFNoC DDC/DUC blocks. We are working on a fix and expect to have in a future release of UHD. Regards, Nate Temple On Mon, Jan 28, 2019 at 10:11 AM Andrew Danowitz via USRP-users < usrp-users@lists.ettus.com> wrote: > I have an RFNOC blo

[USRP-users] 2 DMAfifo blocks?

Is it possible to have two different DMAFifo RFNoC blocks on an X310? I am not worried about the resources so much as how to implement it (I know that I cannot add it to the uhd_image_builder as it is a special case). Thanks. ___ USRP-users mailing l

Re: [USRP-users] 2 DMAfifo blocks?

On Mon, Jan 28, 2019 at 3:42 PM Jason Matusiak via USRP-users < usrp-users@lists.ettus.com> wrote: > Is it possible to have two different DMAFifo RFNoC blocks on an X310? I > am not worried about the resources so much as how to implement it (I know > that I cannot add it to the uhd_image_builder

Re: [USRP-users] Include files missing in and

Hi Rob, On Fri, 2019-01-25 at 17:42 -0500, Rob Kossler wrote: > Why do you compare two instances of "device" with one instance of > "multi_usrp"? Can't the device object have two IP addresses? Nope, can't. That's what multi_usrp was designed for. Device is a single device representation. It *sho

Re: [USRP-users] Live rate changes within an RFNOC block

Hi Andrew, Have you simulated or used chipscope on your block? There is an output from axi rate change called "error_extra_outputs" that can be useful. Does it assert ever assert? If so, that means your user code has output more samples than axi rate change was expecting. If any extra samples come

Re: [USRP-users] 2 DMAfifo blocks?

Hi Jason, Yes you can have two. It will require some hand editing of files. The DmaFIFO connects to the DRAM via an AXI interconnect (x300/ip/axi_intercon_2x64_128_bd/axi_intercon_2x64_128_bd.bd) in x300_core.v. You will need to edit the BD to add more ports to the interconnect. N3xx has a 4x exam