Hello Allouche,
the "make.py" script was renamed to be the uhd_image_builder.py [1], which
I assume is the one you are referring to when you mention the
"uhd_usrp_builder.py". The fact that your IP is not being correctly picked
up might be related to your makefiles, which you'd have to review
care
The second parameter to the set source is motherboard ID, so the sources are
set on that motherboard as you have specified, but the board doesnt know if it
is daisy chained or not, it just knows for that motherboard, use the external
port as its source...
> On May 14, 2018 at 6:58 PM harfan rya
Hi Rob,
Thanks for your explanation,
However i have modified the configuration using external clock source (sync
box), it seems work better, and the error message has gone. But another
problem comes out, after several minutes the application started, there is
an overload of message.
My bes
Hi Jon. First of all, you should not be using a SG1 image with the E313.
All E313s contain E310s with Speed Grade 3 FPGAs.
The behavior you describe is a result of a corrupted bit in the AVR EEPROM
firmware that results in the power on sequence requiring the power button
to be pushed. This corr
Hello,
I'm trying to rebuild the E310 file system as shown here:
http://files.ettus.com/manual/page_usrp_e3x0.html#e3x0_image_building .
I had to make one minor change, my network doesn't allow me to pull files from
"git://" sites, so I used the https:// mirror for all of the repo fetching.
I
