Hi,
I have downloaded from the FPGA image repository
files.ettus.com/binaries/images/ the image set for UHD version 3.9.7
(uhd-images_003.009.007-release.tar.gz). The file looks huge (64MB rather than
25M) and contains some images that cannot talk with UHD 3.9.7 host side (e.g.,
XG and HG imag
Jon,
Like I mentioned earlier, I've used E310's for TDOA measurements with
success. I do have the same initial offset issue, but I can either a)
compute the offset and manually correct for it, or b) stop and restart the
stream, and the offset disappears.
If the offset is drifting, you are not usi
I have been trying to use Vivado lab to return my N210 to a useable state and
am looking for some help.
I see the green light lit on the Xilinx USB to JTAG adaptor and the connection
seems good, however, I keep getting errors during the programming of the
EE_PROM. Below is what I constantly se
Hi,I have a USRP1 Rev2 board and a FLEX900 dboard. The flex900 works fine with
USRP1 Rev4.5, but wont work with USRP1 Rev2.
I read somewhere that I shoud modify the flex900 to make it work with USRP1
Rev2.
The problem is I read two different tips...
in "https://files.ettus.com/manual/page_dboard
On 10/23/2017 02:16 PM, Angilberto Muniz Sb via USRP-users wrote:
Hi,
I have a USRP1 Rev2 board and a FLEX900 dboard. The flex900 works fine
with USRP1 Rev4.5, but wont work with USRP1 Rev2.
I read somewhere that I shoud modify the flex900 to make it work with
USRP1 Rev2.
The problem is I r
Hello Angilberto Muniz:
An alternative to this is to modify the USRP 1 motherboard (instead of the
dauthgerboard). There used to be a GNURadio wiki page about this
("USRPSerialBelow500"), but it is apparently gone. You can still find some
old e-mail archives and Chinese articles (with images) rega
If anyone has that wiki page archived, I'd love to see it as I have a
very early USRP1 that I meant to modify but never got around to it.
IIRC, it was to add a missing clock signal to the daughterboard
connector. In the meantime, I'll dig for the resources that Kyeong
mentioned.
On 10/23/201
The AB and BA frontend configurations are not supported with RFNOC (or
UHD 3.10) on the X-Series. In a nutshell, it's because the original
drivers were registering phony frontends to simulate switching between
them, but they all go to the same connectors. The RFNoC architecture
doesn't let us easil
Daniel,
FFT controls happen through the 'shift', 'direction', and 'scaling'
properties. See, e.g., here:
https://github.com/EttusResearch/uhd/blob/ec9138eb6634b0af106762832c7518c887576a94/host/include/uhd/rfnoc/blocks/fft.xml#L71-L82
The control word is constructed in the block from those setting
If this is on the RFNoC branch, you will need to modify the
radio_e300.xml file to make it have one channel.
-- Martin
On 10/09/2017 06:31 PM, Xingjian Chen via USRP-users wrote:
> Hi,
>
> I added some IP cores in E312 FPGA codes and have to delete one radio
> channel for saving some resources s
Simon,
the E310 can't support rates > 10 Msps into the ARM. The idea of RFNoC
is to offload the signal processing into the FPGA, so the ARM core
doesn't have to do the signal processing.
As for your segfault, the stack trace is not really useful -- generally
a clue that there's a mis-linking goin
Hi Kyeong,Thanks for the info.. I'll try to find the article..
Regards,
Angilberto.
Em segunda-feira, outubro 23, 2017, 5:08 PM, Kyeong Su Shin
escreveu:
Hello Angilberto Muniz:
An alternative to this is to modify the USRP 1 motherboard (instead of the
dauthgerboard). There used to be a G
Thankx Marcus -- I´ll try that too...
Here is the link for the article, John..
http://gnuradio.microembedded.com/usrpserialbelow500
Angilberto. ___
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Hi Daniel,
thank you for your reply.
This is test code:
I'm using tow E312 to estimate the arrive time difference between received
signals.The
program is explained as follows:
uhd::usrp::multi_usrp::sptr UsrpDev = uhd::usrp::multi_usrp::make(“”);
UsrpDev->set_time_source("gpsdo");
UsrpDev->set_clo
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