From what I recall of the architecture that’s the case. The AD9361 has built in
DSP functions.
Sent from my iPhone
> On Jun 26, 2020, at 12:37 AM, David Carsenat wrote:
>
>
> OK thanks. So you confirm the link between UHD sample rate and AD93xx sample
> rate ?
>
> David
>
>> Le ven. 26 j
OK thanks. So you confirm the link between UHD sample rate and AD93xx
sample rate ?
David
Le ven. 26 juin 2020 à 00:23, Marcus D. Leech via USRP-users <
usrp-users@lists.ettus.com> a écrit :
> On 06/25/2020 03:04 PM, David Carsenat via USRP-users wrote:
> > Hello.
> > We are trying to make a sim
On 06/25/2020 03:04 PM, David Carsenat via USRP-users wrote:
Hello.
We are trying to make a simple RX on TX loopback by changing the FPGA
image.
We get it by adding a wire between the DDC output and DUC input, but
we are still limited by the sample rate we specify via UHD.
We have specified th
Hello.
We are trying to make a simple RX on TX loopback by changing the FPGA image.
We get it by adding a wire between the DDC output and DUC input, but we are
still limited by the sample rate we specify via UHD.
We have specified the analog bandwidth at 56 MHz, and the master
clock rate at 60 MHz
