Hey Dmitry,
for the DDC case, we always use the timestamp for the first package. If
your decim is 2, then every other timestamp is effectively discarded.
The counter your referring to is thus more relevant for the DUC use case.
Cheers,
Martin
On 01/16/2018 01:51 AM, Дмитрий Михайличенко via USRP
2018-01-16 3:31 GMT+03:00 Martin Braun via USRP-users <
usrp-users@lists.ettus.com>:
> On 01/11/2018 01:38 AM, Дмитрий Михайличенко via USRP-users wrote:
> > Hi,
> >
> > I am trying to understand timestamp tracking in FPGA and noticed one
> > possible issue in axi_rate_change.v module .
> >
> > VI
On 01/11/2018 01:38 AM, Дмитрий Михайличенко via USRP-users wrote:
> Hi,
>
> I am trying to understand timestamp tracking in FPGA and noticed one
> possible issue in axi_rate_change.v module .
>
> VITA time in packet headers is counted in ticks of master clock
> frequency, i.e. 200 MHz. For me it
Hi,
I am trying to understand timestamp tracking in FPGA and noticed one
possible issue in axi_rate_change.v module .
VITA time in packet headers is counted in ticks of master clock frequency,
i.e. 200 MHz. For me it looks like axi_rate_change adjusts time by adding
time from the first packet in
