Hello All,
I’ve got an update regarding synchronization inside of FPGA between Tx and Rx
after overflows.
I’ve checked that with measurements and there was no synchronization loss
between replay block working on Tx side and our RFNoC block that selects
samples on the Rx side, which is inserted
Hello Martin,
Somehow I missed your reply.
In the meantime I’ve started from implementing what you described in the first
point.
If anyone is interested - it appeared that ‘keep_one_in_n‘ was a very good
starting point. I left the last state\
machine that is responsible for forming output pack
Hey Piotr,
it took me a bit to respond because this is tricky question. And I still
don't have a great answer, but I also don't want to let you hang.
A few thoughts:
- Maybe you just want to write an RFNoC block that drops samples in a
regular pattern for you. That way you wouldn't rely on timed
Hi Piotr,
I just noticed that I had a typo in my reply to you.
Regarding the statement,
> you could just set it to transmit samples as soon as it gets them (i.e. the
> wr_data_en signal would be equal to the inverted FIFO empty flag)
I called the control signal ‘wr_data_en‘, thinking of the en
Hi Piotr,
I’m not familiar enough with RFNoC to be of assistance there, but your thought
about controlling the flow of samples between the ADC and the radio block seems
to have some merit. We frequently timestamp the sample stream so that we can
then tell the radio to, “Give me samples betwee
