Hi Piotr, I just noticed that I had a typo in my reply to you.
Regarding the statement, > you could just set it to transmit samples as soon as it gets them (i.e. the > wr_data_en signal would be equal to the inverted FIFO empty flag) I called the control signal ‘wr_data_en‘, thinking of the enable signal on the downstream block. From the perspective of the output of the FIFO, it would be the rd_en signal that is equal to the inverted FIFO empty flag. So, whenever the FIFO has data in it (i.e. “not empty“) the rd_enable will be active. It will be deactivated when the FIFO is empty. If you need to generate a data_vld signal (to drive ‘wr_data_en‘ on the downstream block), you can do so by delaying a copy of rd_enable by a clock tick or two, depending on whether the output of the FIFO is registered. Cheers, Mike
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