Hi Piotr,
I’m not familiar enough with RFNoC to be of assistance there, but your thought
about controlling the flow of samples between the ADC and the radio block seems
to have some merit. We frequently timestamp the sample stream so that we can
then tell the radio to, “Give me samples between time A and time B.”
Substituting your trigger for the timestamps, you essentially have the same
circuit. The easiest way to do it might be by editing the x410_ps_rfdc_bd
block design in Vivado IP Integrator, and then exporting the new block design
back to x410_ps_rfdc_bd.tcl so it will be built when you do a ‘make’. If you
don’t want anything sent to the PC between triggers, the basic implementation
would be to put an AXI Stream FIFO between the ADC and radio block. The input
valid signal would be driven by the trigger, such that it would ignore the
incoming samples when the trigger was low, and write the samples to the buffer
when the trigger was high. Depending on the configuration of the FIFO buffer,
you could use it in ‘packet’ mode to send the whole buffer once there were a
certain number of samples in it; OR, if you know that the PC can handle the new
reduced rate without flow control, you could just set it to transmit samples as
soon as it gets them (i.e. the wr_data_en signal would be equal to the inverted
FIFO empty flag).
I’m sorry I don’t have an RFNoC-related answer. We don’t use RFNoC, and I
usually design the data-paths based on the requirements of other processing
blocks in the design, and of the downstream equipment, exactly as you described
in your question.
I’m happy to elaborate further if you have any questions.
Hope this helps,
Mike
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